Changes between Version 12 and Version 13 of Writing Rules/RISC
- Timestamp:
- Jan 9, 2008, 5:14:05 PM (17 years ago)
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Writing Rules/RISC
v12 v13 167 167 for (uint32_t i = 0 ; i < iss_t::n_irq ; i++) { 168 168 new(&p_irq[i]) sc_in<bool> ("irq", i) ; 169 } 169 } 170 m_ins_asked = false ; 171 m_data_asked = false ; 170 172 SC_METHOD(transition); 171 173 dont_initialize(); … … 181 183 iss_t m_iss ; 182 184 bool m_ins_asked ; 183 enum InsAccessType m_ins_type ; 184 uint32_t m_ins_address ; 185 bool m_mem_asked ; 186 enum DataAccessType m_mem_type ; 187 uint32_t m_mem_address ; 188 uint32_t m_mem_wdata ; 185 bool m_data_asked ; 189 186 190 187 ///////////////////////// … … 195 192 return; 196 193 } 194 197 195 bool frozen = false; 198 m_iss.getDataRequest(m_mem_asked, 199 m_mem_type, 200 m_mem_address, 201 m_mem_wdata ); 202 m_iss.getInstructionRequest(m_ins_asked, 203 m_ins_type, 204 m_ins_address ); 196 205 197 if ( m_ins_asked ) { 206 198 if ( p_icache.frz.read() ) frozen = true; 207 199 else m_iss.setInstruction(p_icache.berr, p_icache.ins.read()) 208 200 } 209 if ( m_mem_asked ) { 210 if ( p_dcache.frz.read()) frozen = true; 211 else m_iss.setRdata(false, p_dcache.rdata.read()); 201 202 if ( m_data_asked ) { 203 if ( p_dcache.frz.read() ) frozen = true; 204 m_iss.setRdata(p_dcache.berr.read(), p_dcache.rdata.read()); 212 205 } 206 213 207 if ( frozen || m_iss.isBusy() ) { // Processor frozen or busy 214 208 m_iss.nullStep(); 215 209 } else { // Execute one instruction: 216 uint32_t irqword = 0;217 for ( size_t i=0; i<(size_t)iss_t::n_irq; i++ ) { if (p_irq[i].read()) irqword |= (1<<i); }218 m_iss.setIrq(irqword);219 210 m_iss.step(); 220 } // end transition() 211 } 212 213 // report interrupts 214 uint32_t irqword = 0; 215 for ( size_t i=0; i<(size_t)iss_t::n_irq; i++ ) { if (p_irq[i].read()) irqword |= (1<<i); } 216 m_iss.setIrq(irqword); 217 218 // report asynchronous bus error 219 if ( p_dcache.berr.read() ) m_iss.setWriteBerr() ; 220 221 } // end transition() 221 222 222 223 ////////////////////////////// 223 224 void genMoore() 224 { 225 p_icache.req = m_ins_asked; 226 p_icache.type = m_ins_type ; 227 p_icache.adr = m_ins_address; 228 p_dcache_req = m_mem_asked ; 229 p_dcache_type = m_mem_type ; 230 p_dcache.adr = m_mem_address; 231 p_dcache.wdata = m_mem_wdata; 225 { 226 bool ins_req ; 227 enum InsAccessType ins_type ; 228 uint32_t ins_address ; 229 bool data_req ; 230 enum DataAccessType data_type ; 231 uint32_t data_address ; 232 uint32_t data_wdata ; 233 234 m_iss.getDataRequest( data_req, data_type, data_address, data_wdata ) ; 235 m_iss.getInstructionRequest( ins_req, ins_type, ins_address ) ; 236 237 p_icache.req = ins_asked ; 238 p_icache.type = ins_type ; 239 p_icache.adr = ins_address; 240 p_dcache_req = data_req ; 241 p_dcache_type = data_type ; 242 p_dcache.adr = data_address; 243 p_dcache.wdata = data_wdata; 232 244 } // end genMoore 233 245 }}}