Changes between Version 16 and Version 17 of Writing Rules/RISC

Timestamp:

Jan 10, 2008, 6:37:58 PM (17 years ago)

Author:

alain

Comment:

--

Writing Rules/RISC

@@ -333 +333 @@
 ///////  member variables
 tlmt_time  m_time ;
+sc_event m_rsp_received ;
 iss_t  m_iss ;
+uint32_t  m_rsp_error ;
 uint32_t  m_dcache_nlines ;
 uint32_t  m_dcache_nwords ;
@@ -356 +358 @@
             m_iss.nullStep() ;
         } else {
+            /////////// cache access
             m_iss.getInstructionRequest(icache_req.valid,
                           icache_req.type,
-                          icache_req.mode, 
                           icache_req.address) ;
             m_iss.getDataRequest(dcache_req.valid, 
-                          dcache_req.type, 
-                          dcache_req.mode,
+                          dcache_req.type,
                           dcache_req.address, 
                           dcache_req.wdata) 
             xcacheAccess(&icache_req, &dcache_req, &xcache_rsp) ;
-            m_iss.setInstruction(xcache_rsp.iber, xcache_rsp.instruction) ;
-            if(dcache_req.isRead()) m_iss.setRdata(xcache_rsp.dber, xcache_rsp.rdata) ;
+            if ( icache_req.valid ) m_iss.setInstruction(xcache_rsp.iber, xcache_rsp.instruction) ;
+            if ( dcache_req.valid ) m_iss.setDataResponse(xcache_rsp.dber, xcache_rsp.rdata) ;
+            //////// handling interrupts
             irqword = 0 ;
             for ( size_t i = 0 ; i < iss_t ::n_irq ; i++) {
                 if( m_irqpending[i] && m_irqtime[i] <= get_time()) irqword  |= (1<<i);
                }
-            m_iss.setIrq(irqword) ;     
+            m_iss.setIrq(irqword) ;
+            ///////// handling asynchronous bus error
+            if ( m_write_error ) {
+                setWriteBerr() ;
+                m_write_error = false ;
+            }   
             m_iss.step() ;
         } // end cycle
@@ -392 +399 @@
     } // end cacheAccess()
 
-
 ////////////////////////////
 void  rspReceived(vci_rsp_t rsp,
               uint32_t  time)
     {
-    ...
+    if ( rsp.cmd == VCI_CMD_write ) {  // asynchronous bus error signaling
+        m_write_error = ( rsp.error != 0 ) ;
+    }
+    if ( rsp.cmd == VCI_CMD_READ ) {  // time update & cache activation
+        m_time.updateTime( time + rsp.length ) ;
+        notify( m_rsp_received ) ;
+    } 
     } // end rspReceived()