Changes between Version 1 and Version 2 of Writing Rules/RISC

Timestamp:

Jan 7, 2008, 1:09:00 PM (16 years ago)

Author:

alain

Comment:

--

Writing Rules/RISC

@@ -23 +23 @@
 || ISS MIPSR3000        || CABA Model MIPS          || TLM-T Model MIPS          || PV Model MIPS  ||
 || ISS PPC405              || CABA Model PPC            || TLM-T Model PPC            || PV Model PPC   ||
-|| ISS OpenRISC       || CABA Model OpenRISC || TLM-T Model OpenRISC || PV Model MIPS  ||
+|| ISS OpenRISC       || CABA Model OpenRISC || TLM-T Model OpenRISC || PV Model OpenRISC  ||
 
 The method has been demonstrated for the MIPSR3000 and PPC 405 processors, and can be simply extended to the OpenRISC, Sparc, Nios, and MicroBLAZE processors.
@@ -38 +38 @@
 
 
-* '''inline void reset()''' 
+ * '''inline void reset()''' 
 This function reset all registers defining the processor internal state.
 
@@ -50 +50 @@
 This function performs one internal step of a long instruction.
  
- * '''inline void getInstructionRequest (bool & req , enum InsAccessType        & type, uint32_t & address)'''
+ * '''inline void getInstructionRequest (bool & req , enum !InsAccessType       & type, uint32_t & address)'''
 This function is used by the wrapper to obtain from the ISS the instruction request parameters. The ‘’’req’’’ parameter is true when there is a valid request. The ‘’’address’’’ parameter is the instruction address. The  ‘’’type’’’ parameter can have the values defined below:  
 {{{
@@ -59 +59 @@
 }}}
 
- * '''inline void getDataRequest (bool &req , enum DataAccessType       & type, uint32_t & address, uint32_t & wdata)'''
+ * '''inline void getDataRequest (bool &req , enum !DataAccessType      & type, uint32_t & address, uint32_t & wdata)'''
 This function is used by the wrapper to obtain from the ISS the data request parameters. The ‘’’req’’’ parameter is true when there is a valid request. The ‘’’address’’’ parameter is the data address, and the ‘’’wdata’’’ parameter is the data value to be written. The  ‘’’type’’’ parameter is  defined below :
 {{{
 enum DataAccessType {
-RW ,   // Read Word Cached
-RH ,  // Read Half Cached
-RB  ,  // Read Byte Cached
-RZ ,   // Cache Line Invalidate 
-RWU ,  // Read Word Uncached
-RHU ,  // Read Half Uncached
-RBU ,  // Read Byte Uncached
-WW ,  // Write Word
-WH ,  // Write Half
-WB ,  // Write Byte
-SC ,  // Store Conditional word
-LL ,  // Load Linked word
+    RW ,   // Read Word Cached
+    RH ,  // Read Half Cached
+    RB  ,  // Read Byte Cached
+    RZ ,   // Cache Line Invalidate 
+    RWU ,  // Read Word Uncached
+    RHU ,  // Read Half Uncached
+    RBU ,  // Read Byte Uncached
+    WW ,  // Write Word
+    WH ,  // Write Half
+    WB ,  // Write Byte
+    SC ,  // Store Conditional Word
+    LL ,  // Load Linked Word
 } 
 }}}
@@ -94 +94 @@
 As an example, we present the general structure of the MIPS R3000 ISS, as depicted in the chronogram of figure 2. The instruction fetch, instruction decode, and instruction execution are done in one cycle. A specific register ‘’’r_npc’’’ is introduced to model the delayed branch mechanism : the instruction following a branch instruction is always executed. The load instructions are executed in two cycles, as those instructions require two cache access (one for the instruction, one for the data). The ISS can issue two simultaneous request for the instruction cache, and the data cache, but those requests are done for different instructions. 
 
-
+[[Image(chronogramme.png, nolink)]]