| 46 | | * '''inline void reset()''' |
| 47 | | |
| 48 | | This function resets all registers defining the processor internal state. |
| 49 | | |
| 50 | | * '''inline bool isBusy()''' |
| 51 | | |
| 52 | | This function is only used by timed wrappers (CABA & TLM-T). In RISC processors, most instructions have a visible latency of one cycle. But some instructions (such as multiplication or division) can have a visible latency longer than one cycle. This function is called by the CABA and TLM-T wrappers before executing one step : If the processor is busy, the wrapper calls the '''nullStep()''' function. If the processor is available, the wrapper may call the '''step()''' function to execute one instruction. |
| 53 | | |
| 54 | | * '''inline void step()''' |
| 55 | | |
| 56 | | This function executes one instruction. All processor internal registers can be modified. |
| 57 | | |
| 58 | | * '''inline void nullStep()''' |
| 59 | | |
| 60 | | This function performs one internal step of a long instruction. |
| 61 | | |
| 62 | | * '''inline void getInstructionRequest (bool & req , uint32_t & address)''' |
| 63 | | |
| 64 | | This function is used by the wrappers to obtain from the ISS the instruction request parameters. The '''req''' parameter is true when there is a valid request. The '''address''' parameter is the instruction address. |
| 65 | | |
| 66 | | * '''inline void getDataRequest (bool &req , enum !DataAccessType & type, uint32_t & address, uint32_t & wdata)''' |
| 67 | | |
| 68 | | This function is used by the wrapper to obtain from the ISS the data request parameters. The '''req''' parameter is true when there is a valid request. The '''address''' parameter is the data address, and the '''wdata''' parameter is the data value to be written. The '''type''' parameter is defined below : |
| 69 | | {{{ |
| 70 | | enum DataAccessType { |
| 71 | | READ_WORD, // Read Word |
| 72 | | READ_HALF, // Read Half |
| 73 | | READ_BYTE, // Read Byte |
| 74 | | LINE_INVAL, // Cache Line Invalidate |
| 75 | | WRITE_WORD, // Write Word |
| 76 | | WRITE_HALF, // Write Half |
| 77 | | WRITE_BYTE, // Write Byte |
| 78 | | STORE_COND, // Store Conditional Word |
| 79 | | READ_LINKED, // Load Linked Word |
| 80 | | } |
| 81 | | }}} |
| 82 | | |
| 83 | | * '''inline void setInstruction (bool error, uint32_t ins)''' |
| 84 | | |
| 85 | | This function is used by the wrapper to transmit to the ISS, the instruction to be executed ('''ins''' parameter). In case of exception (bus error), the '''error''' parameter is set. |
| 86 | | |
| 87 | | * '''inline void setDataResponse (bool error, uint32_t rdata)''' |
| 88 | | |
| 89 | | This function is used by the wrapper to transmit to the ISS, the response to the data request. In case of a read request, the '''rdata''' parameter contains the read value. In case of exception (bus error), the '''error''' parameter is set. |
| 90 | | |
| 91 | | In any case, this function must reset the ISS data request. |
| 92 | | |
| 93 | | * '''inline void setWriteBerr ()''' |
| 94 | | |
| 95 | | This function is used by the wrapper to signal asynchronous bus errors, in case of a write acces, that is non blocking for the processor. |
| 96 | | |
| 97 | | * '''inline void setIrq (uint32_t irq)''' |
| 98 | | |
| 99 | | This function is used by the wrapper to signal the current value of the interrupt lines. For each processor, the number of interrupt lines must be defined by the ISS static variable '''n_irq'''. |
| 100 | | |
| | 46 | API is defined in a ~~[wiki:Component/IssApi dedicated document]~~. It evolved to a new version: [wiki:Component/Iss2Api ISS2 API] |
| | 47 | |
