Changes between Version 5 and Version 6 of Writing Rules/RISC


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Timestamp:
Jan 7, 2008, 6:11:37 PM (16 years ago)
Author:
alain
Comment:

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  • Writing Rules/RISC

    v5 v6  
    5050This function performs one internal step of a long instruction.
    5151 
    52  * '''inline void getInstructionRequest (bool & req , enum !InsAccessType       & type, uint32_t & address)'''
     52 * '''inline void getInstructionRequest (bool & req , enum !InsAccessType & type, uint32_t & address)'''
    5353This function is used by the wrapper to obtain from the ISS the instruction request parameters. The '''req''' parameter is true when there is a valid request. The '''address''' parameter is the instruction address. The  '''type''' parameter can have the values defined below: 
    5454{{{
    … …  
    5959}}}
    6060
    61  * '''inline void getDataRequest (bool &req , enum !DataAccessType      & type, uint32_t & address, uint32_t & wdata)'''
     61 * '''inline void getDataRequest (bool &req , enum !DataAccessType  & type, uint32_t & address, uint32_t & wdata)'''
    6262This function is used by the wrapper to obtain from the ISS the data request parameters. The '''req''' parameter is true when there is a valid request. The '''address''' parameter is the data address, and the '''wdata''' parameter is the data value to be written. The  '''type''' parameter is  defined below :
    6363{{{
    … …  
    133133
    134134The CABA modeling for a complete CPU (processor + cache) is presented in figure 2.
    135 The processor ISS is wrapped in the generic CABA wrapper, implemented by the class '''!IssWrapper'''.
    136 This class inherit the class '''!Caba::ModuleBase''', that is the basis for all CABA modules.
    137 The class '''!IssWrapper''' contains the member variable '''iss''' representing the processor ISS. The type of the '''iss''' variable - defining the type of theprocessor - is specified by the template parameter '''iss_t'''.
     135The processor ISS is wrapped in the generic CABA wrapper, implemented by the class '''!IssWrapper'''..
     136The class '''!IssWrapper''' contains the member variable '''m_iss''' representing the processor ISS. The type of the '''m_iss''' variable - defining the type of the processor - is specified by the template parameter '''iss_t'''.
    138137
    139138[[Image(caba_wrapper.png, nolink)]]
    140139
    141 To communicate with the '''!VciXcache''', the '''!IssWrapper''' class contains two member variables '''p_icache''', of type '''!IcacheProcessorPort''' and '''p_dcache''', of type '''!DcacheProcessorPort'''.
    142 
    143 This class contains also N member variables '''p_irq[i]''', of type '''sc_in<bool>''', representing the interrupt ports. The number N of interrupt ports depends on the wrapped ISS, an is defined by the '''n_irq''' member variable of the '''iss''' object.
    144 
    145 The CABA wrapper is presented below :
     140To communicate with the '''!VciXcache''', the '''!IssWrapper''' class contains two member variables '''p_icache''', of type '''!IcacheProcessorPort''' and '''p_dcache''', of type '''!DcacheProcessorPort'''. It contains also N member variables '''p_irq[i]''', of type '''sc_in<bool>''', representing the interrupt ports. The number N of interrupt ports depends on the wrapped ISS, an is defined by the '''n_irq''' member variable of the '''iss''' object.
     141
     142The SystemC code for the generic CABA wrapper is presented below :
    146143
    147144{{{
    … …  
    161158///////// constructor ///////////
    162159IssWrapper(sc_module_name insname,
    163          int    ident ) :
     160           int  ident ) :
    164161    BaseModule(insname),
    165162    p_icache("icache"),
    … …  
    182179iss_t  m_iss ;
    183180bool  m_ins_asked ;
    184 enum ins_access_type  m_ins_type ;
    185 enum access_mode  m_ins_mode ;
    186 uint32_t  m_ins_addr ;
     181enum InsAccessType  m_ins_type ;
     182uint32_t  m_ins_address ;
    187183bool  m_mem_asked ;
    188 enum data_access_type  m_mem_type ;
    189 enum access_mode  m_mem_mode ;
    190 uint32_t  m_mem_addr ;
     184enum DataAccessType  m_mem_type ;
     185uint32_t  m_mem_address ;
    191186uint32_t  m_mem_wdata ;
    192187
    … …  
    201196    m_iss.getDataRequest(m_mem_asked,
    202197                m_mem_type,
    203                 m_mem_mode,
    204                 m_mem_addr,
     198                m_mem_address,
    205199                m_mem_wdata );
    206200    m_iss.getInstructionRequest(m_ins_asked,
    207201                m_ins_type,
    208                 m_ins_mode,
    209                 m_ins_addr );
     202                m_ins_address );
    210203    if ( m_ins_asked ) {
    211204        if ( p_icache.frz.read() ) frozen = true;
    … …  
    242235= F) TLM-T modeling =
    243236
    244 The TLM-T modeling for a complete CPU (processor + cache) is presented in figure 4.
    245 To increase the simulation speed, the TLM-T wrapper is the cache controler itself, and it is implemented as the class ‘’’ !VciXcache’’’. This class contains the SC_THREAD ‘’’execLoop()’’’’ implementing the PDES process, and the ‘’’m_time’’’ member variable implementing the associated local clock. The class ‘’’ !VciXcache’’’ inherit the class ‘’’ !Tlmt::ModuleBase’’’, that is the basis for all TLM-T modules.
     237The TLM-T modeling for a complete CPU (processor + cache) is presented in figure 3.
     238To increase the simulation speed, the TLM-T wrapper is the cache controler itself, and it is implemented as the class ''' !VciXcache'''. This class contains the SC_THREAD '''execLoop()''' implementing the PDES process, and the '''m_time''' member variable implementing the associated local clock. The class '''!VciXcache''' inherit the class '''!Tlmt::ModuleBase''', that is the basis for all TLM-T modules.
    246239This class contains the member variable ‘’’iss’’’ representing the processor ISS. The type of the ‘’’iss’’’ variable is defined by the template parameter ‘’’iss_t’’’.
    247240