Changes between Version 6 and Version 7 of Writing Rules/RISC


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Timestamp:
Jan 7, 2008, 6:28:18 PM (16 years ago)
Author:
alain
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  • Writing Rules/RISC

    v6 v7  
    138138[[Image(caba_wrapper.png, nolink)]]
    139139
    140 To communicate with the '''!VciXcache''', the '''!IssWrapper''' class contains two member variables '''p_icache''', of type '''!IcacheProcessorPort''' and '''p_dcache''', of type '''!DcacheProcessorPort'''. It contains also N member variables '''p_irq[i]''', of type '''sc_in<bool>''', representing the interrupt ports. The number N of interrupt ports depends on the wrapped ISS, an is defined by the '''n_irq''' member variable of the '''iss''' object.
     140To communicate with the '''!VciXcache''', the '''!IssWrapper''' class contains two member variables '''p_icache''', of type '''!IcacheProcessorPort''' and '''p_dcache''', of type '''!DcacheProcessorPort'''. It contains also N member variables '''p_irq[i]''', of type '''sc_in<bool>''', representing the interrupt ports. The number N of interrupt ports depends on the wrapped ISS, an is defined by the '''n_irq''' member variable of the '''iss_t''' class.
    141141
    142142The SystemC code for the generic CABA wrapper is presented below :
     
    236236
    237237The TLM-T modeling for a complete CPU (processor + cache) is presented in figure 3.
    238 To increase the simulation speed, the TLM-T wrapper is the cache controler itself, and it is implemented as the class ''' !VciXcache'''. This class contains the SC_THREAD '''execLoop()''' implementing the PDES process, and the '''m_time''' member variable implementing the associated local clock. The class '''!VciXcache''' inherit the class '''!Tlmt::ModuleBase''', that is the basis for all TLM-T modules.
    239 This class contains the member variable ‘’’iss’’’ representing the processor ISS. The type of the ‘’’iss’’’ variable is defined by the template parameter ‘’’iss_t’’’.
    240 
    241 
    242 
    243 
    244 
    245 
    246 
    247 
    248 
    249 
    250 FIGURE 4
    251 
    252 The class ‘’’ !VciXcache’’’ contain a member variable p_vci, of type ‘’’!VciInitPort’’’, to send VCI command packets, and receive VCI response packets.
    253 This class contains also N member variables ‘’’p_irq[i]’’’, of type ‘’’ !IrqInPort’’’, representing the interrupt inputs. The number N of interrupt ports depends on the wrapped ISS, an is defined by the ‘’’n_irq’’’ member variable of the ‘’’iss’’’ object.
    254 
    255 The ‘’’execLoop()’’’ function contains an infinite loop. One iteration in this loop corresponds to one cycle for the local clock, or more in case of MISS, as the thread is suspended in case of MISS.
    256 
    257 The cache behavior is specifically described by the ‘’’cacheAccess()’’’ method, that is a member variable of the class ‘’’ !VciXcache’’’. This function is called in the main execution loop (i.e. at each cycle). This function has the following prototype :
     238To increase the simulation speed, the TLM-T wrapper is the cache controler itself, and it is implemented as the class ''' !VciXcache'''. This class contains the SC_THREAD '''execLoop()''' implementing the PDES process, and the '''m_time''' member variable implementing the associated local clock. The class '''!VciXcache''' inherit the class '''Tlmt::!ModuleBase''', that is the basis for all TLM-T modules.
     239This class contains the member variable '''m_iss''' representing the processor ISS. The type of the '''m_iss''' variable is defined by the template parameter '''iss_t'''.
     240
     241[[Image(tlmt_wrapper.png, nolink)]]
     242
     243The class '''!VciXcache''' contain a member variable '''p_vci''', of type '''!VciInitPort''', to send VCI command packets, and receive VCI response packets.
     244This class contains also N member variables '''p_irq[i]''', of type '''!SynchroInPort''', representing the interrupt inputs. The number N of interrupt ports depends on the wrapped ISS, an is defined by the ‘’’n_irq’’’ member variable of the '''iss_t''' class.
     245
     246The '''execLoop()''' function contains an infinite loop. One iteration in this loop corresponds to one cycle for the local clock, (or more, as the thread is suspended in case of MISS).
     247
     248The cache behavior is specifically described by the '''cacheAccess()''' method, that is a member function of the class '''!VciXcache''', and is called by '''execLoop()'''  at each cycle. This function has the following prototype :
    258249{{{
    259250void cacheAccess(icache_request_t  *ireq,