Changes between Version 7 and Version 8 of Writing Rules/RISC

Timestamp:

Jan 7, 2008, 6:38:48 PM (17 years ago)

Author:

alain

Comment:

--

Writing Rules/RISC

@@ -224 +224 @@
 p_icache.type = m_ins_type ;
 p_icache.mode = m_ins_mode ;
-p_icache.adr = m_ins_addr;
+p_icache.adr = m_ins_address;
 p_dcache_req = m_mem_asked ;
 p_dcache_type = m_mem_type ;
 p_dcache_mode = m_mem_mode ;
-p_dcache.adr = m_mem_addr;
+p_dcache.adr = m_mem_address;
 p_dcache.wdata = m_mem_wdata;  
 } // end genMoore
@@ -242 +242 @@
 
 The class '''!VciXcache''' contain a member variable '''p_vci''', of type '''!VciInitPort''', to send VCI command packets, and receive VCI response packets.
-This class contains also N member variables '''p_irq[i]''', of type '''!SynchroInPort''', representing the interrupt inputs. The number N of interrupt ports depends on the wrapped ISS, an is defined by the ‘’’n_irq’’’ member variable of the '''iss_t''' class.
+This class contains also N member variables '''p_irq[i]''', of type '''!SynchroInPort''', representing the interrupt ports. The number N of interrupt ports depends on the wrapped ISS, an is defined by the ‘’’n_irq’’’ member variable of the '''iss_t''' class.
 
 The '''execLoop()''' function contains an infinite loop. One iteration in this loop corresponds to one cycle for the local clock, (or more, as the thread is suspended in case of MISS).
@@ -249 +249 @@
 {{{
 void cacheAccess(icache_request_t  *ireq,
-                dcache_request_t  *dreq,
-                xcache_response_t  *rsp)
+                 dcache_request_t  *dreq,
+                 xcache_response_t  *rsp)
 }}}
 
@@ -257 +257 @@
 class icache_request_t {
 bool  valid ;
-enum ins_access_type  type ;
-enum access_mode  mode ;
+enum InsAccessType  type ;
 uint32_t  address ;
 }
 class dcache_request_t {
 bool  valid ;
-enum data_access_type  type ;
-enum access_mode  mode ;
+enum DataAccessType  type ;
 uint32_t  address ;
 uint32_t  wdata ;
@@ -275 +273 @@
 }
 }}}
-The ‘’’cacheAccess()‘’’ function détermines the actions to be done. 
-In case of data or instruction MISS MISS, the ‘’’cacheAccess()’’’ function send the proper VCI command packet on the ‘’’p_vci’’’ port., and the ‘’’exedcLoop’’’ thread is suspended.
-In case of data write, the the ‘’’cacheAccess()’’’ function send the proper VCI command packet on the ‘’’p_vci’’’ port., but the ‘’’exedcLoop’’’ thread is not suspended.
-
-At each iteration in the execution loop, the ‘’’cacheAccess()’’’ method updates the local clock (variable ‘’’m_time’’’) :
+The '''cacheAccess()''' function détermines the actions to be done. 
+In case of data or instruction MISS, the '''cacheAccess()''' function sends the proper VCI command packet on the '''p_vci''' port, and the '''exedcLoop()''' thread is suspended.
+In case of data write, the the '''cacheAccess()''' function sends the proper VCI command packet on the '''p_vci''' port, but the '''exedcLoop()''' thread is not suspended.
+
+At each iteration in the execution loop, the '''cacheAccess()''' method updates the local clock (variable '''m_time''') :
 • The local time is simply incremented by one cycle, if the cache controller is able to answer immediately to the processor requests.
-• The local time is updated using the date containeded in the VCI response packet in case of MISS
-
-The TLM-T model for the VciXcache module is presented below :
+• The local time is updated using the date containeded in the VCI response packet in case of MISS.?
+
+The SystemC TLM-T model for the VciXcache module is presented below :
 {{{
 template<typename iss_t, typename vci_param>
-class VciXcache<iss_t> : tlmt ::BaseModule {
+class VciXcache<iss_t> : tlmt::BaseModule {
 
 public :