Changes between Version 8 and Version 9 of Writing Rules/RISC

Timestamp:

Jan 7, 2008, 7:46:35 PM (17 years ago)

Author:

alain

Comment:

--

Writing Rules/RISC

@@ -138 +138 @@
 [[Image(caba_wrapper.png, nolink)]]
 
-To communicate with the '''!VciXcache''', the '''!IssWrapper''' class contains two member variables '''p_icache''', of type '''!IcacheProcessorPort''' and '''p_dcache''', of type '''!DcacheProcessorPort'''. It contains also N member variables '''p_irq[i]''', of type '''sc_in<bool>''', representing the interrupt ports. The number N of interrupt ports depends on the wrapped ISS, an is defined by the '''n_irq''' member variable of the '''iss_t''' class.
+To communicate with the '''!VciXcache''', the '''!IssWrapper''' class contains two member variables '''p_icache''', of type '''!IcacheProcessorPort''' and '''p_dcache''', of type '''!DcacheProcessorPort'''. It contains also the member variable '''p_irq''', That is a pointer to an array of ports of type '''sc_in<bool> *'''. This array represents the interrupt ports. The number N of interrupt ports depends on the wrapped processor, an is defined by the '''n_irq''' member variable of the '''iss_t''' class.
 
 The SystemC code for the generic CABA wrapper is presented below :
@@ -150 +150 @@
 
 //////// ports ////////
-sc_in<bool>  p_irq[iss_t ::n_irq] ;
+sc_in<bool>  *p_irq ;
 IcacheProcessorPort  p_icache ;
 DcacheProcessorPort  p_dcache ;
@@ -160 +160 @@
            int  ident ) :
     BaseModule(insname),
-    p_icache("icache"),
-    p_dcache("dcache"),
-    p_resetn("resetn"),
-    p_clk("clk"),
     m_iss(ident)
     {
+    p_icache("icache") ;
+    p_dcache("dcache") ;
+    p_resetn("resetn") ;
+    p_clk("clk") ;
+    for (uint32_t i = 0 ; i < iss_t::n_irq ; i++) { 
+        new(&p_irq[i]) sc_in<bool> ("irq", i) ; 
+    }
     SC_METHOD(transition);
     dont_initialize();
@@ -223 +226 @@
 p_icache.req = m_ins_asked;
 p_icache.type = m_ins_type ;
-p_icache.mode = m_ins_mode ;
 p_icache.adr = m_ins_address;
 p_dcache_req = m_mem_asked ;
 p_dcache_type = m_mem_type ;
-p_dcache_mode = m_mem_mode ;
 p_dcache.adr = m_mem_address;
 p_dcache.wdata = m_mem_wdata;  
@@ -234 +235 @@
 
 = F) TLM-T modeling =
-
 The TLM-T modeling for a complete CPU (processor + cache) is presented in figure 3. 
 To increase the simulation speed, the TLM-T wrapper is the cache controler itself, and it is implemented as the class ''' !VciXcache'''. This class contains the SC_THREAD '''execLoop()''' implementing the PDES process, and the '''m_time''' member variable implementing the associated local clock. The class '''!VciXcache''' inherit the class '''Tlmt::!ModuleBase''', that is the basis for all TLM-T modules.
@@ -273 +273 @@
 }
 }}}
-The '''cacheAccess()''' function détermines the actions to be done. 
-In case of data or instruction MISS, the '''cacheAccess()''' function sends the proper VCI command packet on the '''p_vci''' port, and the '''exedcLoop()''' thread is suspended.
-In case of data write, the the '''cacheAccess()''' function sends the proper VCI command packet on the '''p_vci''' port, but the '''exedcLoop()''' thread is not suspended.
+The '''cacheAccess()''' function détermines the actions to be done :
+ * In case of data or instruction MISS, the '''cacheAccess()''' function sends the proper VCI command packet on the '''p_vci''' port, and the '''exedcLoop()''' thread is suspended.
+ * In case of data write, the the '''cacheAccess()''' function sends the proper VCI command packet on the '''p_vci''' port, but the '''exedcLoop()''' thread is not suspended.
 
 At each iteration in the execution loop, the '''cacheAccess()''' method updates the local clock (variable '''m_time''') :
-• The local time is simply incremented by one cycle, if the cache controller is able to answer immediately to the processor requests.
-• The local time is updated using the date containeded in the VCI response packet in case of MISS.?
+ * The local time is simply incremented by one cycle, if the cache controller is able to answer immediately to the processor requests.
+ * The local time is updated using the date containeded in the VCI response packet in case of MISS.
 
 The SystemC TLM-T model for the VciXcache module is presented below :
@@ -289 +289 @@
 /////// ports ///////
 VciInitiatorPort<vci_param>  p_vci ;
-IrqInPort  p_irq[iss_t ::n_irq] ;
+SynchroInPort  * p_irq ;
 
 /////// constructor /////
@@ -301 +301 @@
           uint32_t  icache_nwords)
     p_vci(« vci », this, &VciXcache::rspReceived, &m_time) ,
-    for (uint32_t i = 0 ; i < iss_t ::n_irq ; i++) { p_irq[i] (« irq », i, this, &VciXcache::irqReceived) ; }
     BaseModule(name),
     m_iss(processorIdent),
     m_time(0)
     {
+    for (uint32_t i = 0 ; i < iss_t::n_irq ; i++) { 
+        new(&p_irq[i])SynchroInPort ("irq", i, this, &VciXcache::irqReceived) ; 
+    }
     m_initiator_index = initiatorIndex ;
     m_counter = 0 ;
@@ -392 +394 @@
     m_irqtime[p_irq[index] = time ;
     } // end irqReceived()
-
-        
-
-
-
+} // end class VciXcache
+}}}     
+
+
+