Changes between Version 105 and Version 106 of Writing Rules/Tlmt

Timestamp:

Mar 2, 2009, 5:39:17 PM (15 years ago)

Author:

alinevieiramello@…

Comment:

--

Writing Rules/Tlmt

@@ -548 +548 @@
 == E.5) VCI target example ==
 {{{
-
+#include "vci_ram.h"
+
+#ifndef VCI_RAM_DEBUG
+#define VCI_RAM_DEBUG 0
+#endif
+
+#define tmpl(x) x VciRam
+
+//////////////////////////////////////////////////////////////////////////////////////////
+// CONSTRUCTOR
+//////////////////////////////////////////////////////////////////////////////////////////
+tmpl(/**/)::VciRam
+           ( sc_core::sc_module_name name,
+             const soclib::common::IntTab &index,
+             const soclib::common::MappingTable &mt,
+             soclib::common::ElfLoader &loader)
+           : sc_module(name),
+           m_mt(mt),
+           m_loader(new soclib::common::ElfLoader(loader)),
+           m_atomic(8), // 8 equals to maximal number of initiator
+           p_vci_target("socket")
+{
+  //register callback fuction
+  p_vci_target.register_nb_transport_fw(this, &VciRam::my_nb_transport_fw);
+  
+  //identification
+  m_tgtid = m_mt.indexForId(index);
+
+  m_segments = m_mt.getSegmentList(index);
+  m_contents = new ram_t*[m_segments.size()];
+  size_t word_size = sizeof(vci_param::data_t);
+  
+  std::list<soclib::common::Segment>::iterator seg;
+  size_t i;
+  for (i=0, seg = m_segments.begin(); seg != m_segments.end(); ++i, ++seg ) {
+    soclib::common::Segment &s = *seg;
+    m_contents[i] = new ram_t[(s.size()+word_size-1)/word_size];
+  }
+  
+  if ( m_loader ){
+    for (i=0, seg = m_segments.begin(); seg != m_segments.end(); ++i, ++seg ) {
+      soclib::common::Segment &s = *seg;
+      m_loader->load(&m_contents[i][0], s.baseAddress(), s.size());
+      for (size_t addr = 0; addr < s.size()/word_size; ++addr )
+        m_contents[i][addr] = le_to_machine(m_contents[i][addr]);
+    }
+  }
+  
+  //initialize the control table LL/SC
+  m_atomic.clearAll();
+
+}
+
+tmpl(/**/)::~VciRam(){}
+
+/////////////////////////////////////////////////////////////////////////////////////
+// Virtual Fuctions  tlm::tlm_fw_transport_if VCI SOCKET
+/////////////////////////////////////////////////////////////////////////////////////
+
+//nb_transport_fw implementation calls from initiators 
+tmpl(tlm::tlm_sync_enum)::my_nb_transport_fw                            // non-blocking transport call through Bus
+                         ( tlm::tlm_generic_payload &payload,           // generic payoad pointer
+                           tlm::tlm_phase &phase,                       // transaction phase
+                           sc_core::sc_time                   &time)    // time it should take for transport
+{
+  // First, find the right segment using the first address of the packet
+  std::list<soclib::common::Segment>::iterator seg;     
+  size_t segIndex;
+  soclib_payload_extension *extension_pointer;
+  payload.get_extension(extension_pointer);
+
+  if(extension_pointer->is_null_message()){
+#if VCI_RAM_DEBUG
+    std::cout << "[RAM " << m_tgtid << "] Receive NULL MESSAGE Time = "  << time.value()  << std::endl;
+#endif
+    return tlm::TLM_COMPLETED;
+  }
+   
+  uint32_t srcid = extension_pointer->get_src_id();
+  uint32_t pktid = extension_pointer->get_pkt_id();
+  uint32_t nwords = payload.get_data_length() / vci_param::nbytes;
+   
+  for (segIndex=0,seg = m_segments.begin(); seg != m_segments.end(); ++segIndex, ++seg ) {
+    soclib::common::Segment &s = *seg;
+    if (!s.contains(payload.get_address()))
+      continue;
+    
+    switch(extension_pointer->get_command()){
+    case soclib::tlmt::VCI_READ_COMMAND:
+      {
+#if VCI_RAM_DEBUG
+        std::cout << "[RAM " << m_tgtid << "] Receive from source "<< srcid << " a read packet " << pktid << " Time = "  << time.value() << std::endl;
+#endif
+
+        vci_param::addr_t address;
+        for (size_t i=0;i<nwords;i++){
+          //if (payload.contig) 
+          address = (payload.get_address()+(i*vci_param::nbytes)) - s.baseAddress(); //XXX contig = TRUE always
+          //else
+          //address = payload.get_address() - s.baseAddress(); //always the same address
+
+          utoa(m_contents[segIndex][address / vci_param::nbytes], payload.get_data_ptr(),(i * vci_param::nbytes));
+
+          //std::cout << "[RAM " << m_tgtid << "] READ address = " << std::hex << (payload.get_address()+(i*vci_param::nbytes)) << " data  = " <<  m_contents[segIndex][address / vci_param::nbytes] << std::endl;
+
+        }
+        
+        payload.set_response_status(tlm::TLM_OK_RESPONSE);
+        phase = tlm::BEGIN_RESP;
+        time = time + (nwords * UNIT_TIME);
+
+#if VCI_RAM_DEBUG
+        std::cout << "[RAM " << m_tgtid << "] Send to source "<< srcid << " a anwser packet " << pktid << " Time = "  << time.value() << std::endl;
+#endif
+        
+        p_vci_target->nb_transport_bw(payload, phase, time);
+        return tlm::TLM_COMPLETED;
+      }
+      break;
+    case soclib::tlmt::VCI_WRITE_COMMAND:
+      {
+#if VCI_RAM_DEBUG
+        std::cout << "[RAM " << m_tgtid << "] Receive from source " << srcid <<" a Write packet "<< pktid << " Time = "  << time.value() << std::endl;
+#endif
+        
+        vci_param::addr_t address;
+        for (size_t i=0; i<nwords; i++){
+          //if(payload.contig)
+          address = (payload.get_address()+(i*vci_param::nbytes)) - s.baseAddress();//XXX contig = TRUE always
+          //else
+          //address = payload.get_address() - s.baseAddress();
+          
+          m_atomic.accessDone(address);
+          
+          uint32_t index   = address / vci_param::nbytes;
+          ram_t *tab       = m_contents[segIndex];
+          unsigned int cur = tab[index];
+          uint32_t mask    = atou(payload.get_byte_enable_ptr(), (i * vci_param::nbytes));
+          
+          tab[index] = (cur & ~mask) | (atou( payload.get_data_ptr(), (i * vci_param::nbytes) ) & mask);
+
+          //std::cout << "[RAM " << m_tgtid << "] WRITE address = " << std::hex << (payload.get_address()+(i*vci_param::nbytes)) << " data  = " <<  tab[index] << std::endl;
+
+        }
+        
+        payload.set_response_status(tlm::TLM_OK_RESPONSE);
+        phase = tlm::BEGIN_RESP;
+        time = time + (nwords * UNIT_TIME);
+        
+#if VCI_RAM_DEBUG
+        std::cout << "[RAM " << m_tgtid << "] Send to source "<< srcid << " a anwser packet " << pktid << " Time = "  << time.value()  << std::endl;
+#endif
+        
+        p_vci_target->nb_transport_bw(payload, phase, time);
+        return tlm::TLM_COMPLETED;
+      }
+      break;
+    case soclib::tlmt::VCI_LINKED_READ_COMMAND:
+      {
+#if VCI_RAM_DEBUG
+        std::cout << "[RAM " << m_tgtid << "] Receive from source " << srcid <<" a Locked Read packet "<< pktid << " Time = " << time.value() << std::endl;
+#endif
+
+        vci_param::addr_t address;
+        for (size_t i=0; i<nwords; i++){
+          //if(payload.contig)
+          address = (payload.get_address()+(i*vci_param::nbytes)) - s.baseAddress();//XXX contig = TRUE always
+          //else
+          //address = payload.get_address() - s.baseAddress();
+
+          utoa(m_contents[segIndex][address / vci_param::nbytes], payload.get_data_ptr(),(i * vci_param::nbytes));
+
+          //std::cout << "[RAM " << m_tgtid << "] LOCKED READ address = " << std::hex << (payload.get_address()+(i*vci_param::nbytes)) << " data  = " <<  m_contents[segIndex][address / vci_param::nbytes] << std::endl;
+
+          m_atomic.doLoadLinked(address, srcid);
+        }
+
+        payload.set_response_status(tlm::TLM_OK_RESPONSE);
+        phase = tlm::BEGIN_RESP;
+        time = time + (nwords * UNIT_TIME);
+
+#if VCI_RAM_DEBUG
+        std::cout << "[RAM " << m_tgtid << "] Send to source "<< srcid << " a anwser packet " << pktid << " Time = "  << time.value()  << std::endl;
+#endif
+
+        p_vci_target->nb_transport_bw(payload, phase, time);
+        return tlm::TLM_COMPLETED;
+      }
+      break;
+    case soclib::tlmt::VCI_STORE_COND_COMMAND:
+      {
+#if VCI_RAM_DEBUG
+        std::cout << "[RAM " << m_tgtid << "] Receive from source " << srcid <<" a Store Conditionnel packet "<< pktid << " Time = "  << time.value() << std::endl;
+#endif
+
+        vci_param::addr_t address;
+        for (size_t i=0; i<nwords; i++){
+          //if(payload.contig)
+          address = (payload.get_address()+(i*vci_param::nbytes)) - s.baseAddress();//XXX contig = TRUE always
+          //else
+          //address = payload.get_address() - s.baseAddress();
+
+          if(m_atomic.isAtomic(address, srcid)){
+            m_atomic.accessDone(address);
+
+            uint32_t index   = address / vci_param::nbytes;
+            ram_t *tab       = m_contents[segIndex];
+            unsigned int cur = tab[index];
+            uint32_t mask    = atou(payload.get_byte_enable_ptr(), (i * vci_param::nbytes));
+
+            tab[index] = (cur & ~mask) | (atou(payload.get_data_ptr(), (i * vci_param::nbytes)) & mask);
+
+            //std::cout << "[RAM " << m_tgtid << "] STORE COND address = " << std::hex << (payload.get_address()+(i*vci_param::nbytes)) << " data  = " <<  tab[index] << std::endl;
+
+            utoa(0, payload.get_data_ptr(),(i * vci_param::nbytes));
+          }
+          else{
+            utoa(1, payload.get_data_ptr(),(i * vci_param::nbytes));
+          }
+        }
+
+        payload.set_response_status(tlm::TLM_OK_RESPONSE);
+        phase = tlm::BEGIN_RESP;
+        time = time + (nwords * UNIT_TIME);
+
+#if VCI_RAM_DEBUG
+        std::cout << "[RAM " << m_tgtid << "] Send to source "<< srcid << " a anwser packet " << pktid << " Time = "  << time.value()  << std::endl;
+#endif
+
+        p_vci_target->nb_transport_bw(payload, phase, time);
+        return tlm::TLM_COMPLETED;
+      }
+      break;
+     default:
+     break;
+    }
+  }
+  
+  //send error message
+  payload.set_response_status(tlm::TLM_COMMAND_ERROR_RESPONSE);
+  
+  phase = tlm::BEGIN_RESP;
+  time = time + nwords * UNIT_TIME;
+  
+#if VCI_RAM_DEBUG
+  std::cout << "[RAM " << m_tgtid << "] Address " << std::hex << payload.get_address() << std::dec << " does not match any segment " << std::endl;
+  std::cout << "[RAM " << m_tgtid << "] Send to source "<< srcid << " a error packet with time = "  << time.value() << std::endl;
+#endif
+  p_vci_target->nb_transport_bw(payload, phase, time);
+  return tlm::TLM_COMPLETED;
+}
 
 }}}