Changes between Version 108 and Version 109 of Writing Rules/Tlmt


Ignore:
Timestamp:
Mar 2, 2009, 6:24:04 PM (14 years ago)
Author:
alinevieiramello@…
Comment:

--

Legend:

Unmodified
Added
Removed
Modified
  • Writing Rules/Tlmt

    v108 v109  
    491491== E.5) VCI target example ==
    492492{{{
    493 #include "vci_ram.h"
    494 
    495 //////////////////////////////////////////////////////////////////////////////////////////
    496 // CONSTRUCTOR
    497 //////////////////////////////////////////////////////////////////////////////////////////
    498 VciRam::VciRam
     493#include "my_target.h"
     494
     495my_target::my_target
    499496( sc_core::sc_module_name name,
    500497  const soclib::common::IntTab &index,
    501   const soclib::common::MappingTable &mt,
    502   soclib::common::ElfLoader &loader)
    503  : sc_module(name),
    504    m_mt(mt),
    505    m_loader(new soclib::common::ElfLoader(loader)),
    506    m_atomic(8), // 8 equals to maximal number of initiator
    507    p_vci_target("socket")
     498  const soclib::common::MappingTable &mt)
     499  : sc_module(name),
     500    m_mt(mt),
     501    p_vci_target("socket")
    508502{
    509503  //register callback fuction
    510   p_vci_target.register_nb_transport_fw(this, &VciRam::my_nb_transport_fw);
     504  p_vci_target.register_nb_transport_fw(this, &my_target::my_nb_transport_fw);
    511505 
    512506  //identification
    513507  m_tgtid = m_mt.indexForId(index);
    514 
    515   //segments
    516   m_segments = m_mt.getSegmentList(index);
    517   m_contents = new ram_t*[m_segments.size()];
    518   size_t word_size = sizeof(vci_param::data_t);
    519   std::list<soclib::common::Segment>::iterator seg;
    520   size_t i;
    521   for (i=0, seg = m_segments.begin(); seg != m_segments.end(); ++i, ++seg ) {
    522     soclib::common::Segment &s = *seg;
    523     m_contents[i] = new ram_t[(s.size()+word_size-1)/word_size];
    524   }
    525  
    526   if ( m_loader ){
    527     for (i=0, seg = m_segments.begin(); seg != m_segments.end(); ++i, ++seg ) {
    528       soclib::common::Segment &s = *seg;
    529       m_loader->load(&m_contents[i][0], s.baseAddress(), s.size());
    530       for (size_t addr = 0; addr < s.size()/word_size; ++addr )
    531         m_contents[i][addr] = le_to_machine(m_contents[i][addr]);
    532     }
    533   }
    534  
    535   //initialize the control table LL/SC
    536   m_atomic.clearAll();
    537 
    538 }
    539 
    540 VciRam::~VciRam(){}
     508}
     509
     510my_target::~my_target(){}
    541511
    542512/////////////////////////////////////////////////////////////////////////////////////
    543513// Virtual Fuctions  tlm::tlm_fw_transport_if (VCI TARGET SOCKET)
    544514/////////////////////////////////////////////////////////////////////////////////////
    545 tlm::tlm_sync_enum VciRam::my_nb_transport_fw                           
    546 ( tlm::tlm_generic_payload &payload,           // generic payoad pointer
    547   tlm::tlm_phase           &phase,             // transaction phase
    548   sc_core::sc_time         &time)              // time it should take for transport
    549 {
    550   // First, find the right segment using the first address of the packet
    551   std::list<soclib::common::Segment>::iterator seg;     
    552   size_t segIndex;
     515tlm::tlm_sync_enum my_target::my_nb_transport_fw          // non-blocking transport call through Bus
     516( tlm::tlm_generic_payload &payload,                      // generic payoad pointer
     517  tlm::tlm_phase           &phase,                       // transaction phase
     518  sc_core::sc_time         &time)                        // time it should take for transport
     519{
    553520  soclib_payload_extension *extension_pointer;
    554521  payload.get_extension(extension_pointer);
    555522
    556   //if soclib command is TLMT_NULL_MESSAGE then message is not threated
     523  //this target does not treat the null message
    557524  if(extension_pointer->is_null_message()){
    558525    return tlm::TLM_COMPLETED;
     
    560527   
    561528  uint32_t srcid = extension_pointer->get_src_id();
    562   uint32_t pktid = extension_pointer->get_pkt_id();
    563529  uint32_t nwords = payload.get_data_length() / vci_param::nbytes;
    564    
    565   for (segIndex=0,seg = m_segments.begin(); seg != m_segments.end(); ++segIndex, ++seg ) {
    566     soclib::common::Segment &s = *seg;
    567     if (!s.contains(payload.get_address()))
    568       continue;
     530  uint32_t address = payload.get_address();
     531 
     532  switch(extension_pointer->get_command()){
     533  case soclib::tlmt::VCI_READ_COMMAND:
     534  case soclib::tlmt::VCI_WRITE_COMMAND:
     535  case soclib::tlmt::VCI_LINKED_READ_COMMAND:
     536  case soclib::tlmt::VCI_STORE_COND_COMMAND:
     537    ...
    569538   
    570     switch(extension_pointer->get_command()){
    571     case soclib::tlmt::VCI_READ_COMMAND:
    572       {
    573 #if VCI_RAM_DEBUG
    574         std::cout << "[RAM " << m_tgtid << "] Receive from source "<< srcid << " a read packet " << pktid << " Time = "  << time.value() << std::endl;
    575 #endif
    576 
    577         vci_param::addr_t address;
    578         for (size_t i=0;i<nwords;i++){
    579           //if (payload.contig)
    580           address = (payload.get_address()+(i*vci_param::nbytes)) - s.baseAddress(); //XXX contig = TRUE always
    581           //else
    582           //address = payload.get_address() - s.baseAddress(); //always the same address
    583 
    584           utoa(m_contents[segIndex][address / vci_param::nbytes], payload.get_data_ptr(),(i * vci_param::nbytes));
    585 
    586           //std::cout << "[RAM " << m_tgtid << "] READ address = " << std::hex << (payload.get_address()+(i*vci_param::nbytes)) << " data  = " <<  m_contents[segIndex][address / vci_param::nbytes] << std::endl;
    587 
    588         }
    589        
    590         payload.set_response_status(tlm::TLM_OK_RESPONSE);
    591         phase = tlm::BEGIN_RESP;
    592         time = time + (nwords * UNIT_TIME);
    593 
    594 #if VCI_RAM_DEBUG
    595         std::cout << "[RAM " << m_tgtid << "] Send to source "<< srcid << " a anwser packet " << pktid << " Time = "  << time.value() << std::endl;
    596 #endif
    597        
    598         p_vci_target->nb_transport_bw(payload, phase, time);
    599         return tlm::TLM_COMPLETED;
    600       }
    601       break;
    602     case soclib::tlmt::VCI_WRITE_COMMAND:
    603       {
    604 #if VCI_RAM_DEBUG
    605         std::cout << "[RAM " << m_tgtid << "] Receive from source " << srcid <<" a Write packet "<< pktid << " Time = "  << time.value() << std::endl;
    606 #endif
    607        
    608         vci_param::addr_t address;
    609         for (size_t i=0; i<nwords; i++){
    610           //if(payload.contig)
    611           address = (payload.get_address()+(i*vci_param::nbytes)) - s.baseAddress();//XXX contig = TRUE always
    612           //else
    613           //address = payload.get_address() - s.baseAddress();
    614          
    615           m_atomic.accessDone(address);
    616          
    617           uint32_t index   = address / vci_param::nbytes;
    618           ram_t *tab       = m_contents[segIndex];
    619           unsigned int cur = tab[index];
    620           uint32_t mask    = atou(payload.get_byte_enable_ptr(), (i * vci_param::nbytes));
    621          
    622           tab[index] = (cur & ~mask) | (atou( payload.get_data_ptr(), (i * vci_param::nbytes) ) & mask);
    623 
    624           //std::cout << "[RAM " << m_tgtid << "] WRITE address = " << std::hex << (payload.get_address()+(i*vci_param::nbytes)) << " data  = " <<  tab[index] << std::endl;
    625 
    626         }
    627        
    628         payload.set_response_status(tlm::TLM_OK_RESPONSE);
    629         phase = tlm::BEGIN_RESP;
    630         time = time + (nwords * UNIT_TIME);
    631        
    632 #if VCI_RAM_DEBUG
    633         std::cout << "[RAM " << m_tgtid << "] Send to source "<< srcid << " a anwser packet " << pktid << " Time = "  << time.value()  << std::endl;
    634 #endif
    635        
    636         p_vci_target->nb_transport_bw(payload, phase, time);
    637         return tlm::TLM_COMPLETED;
    638       }
    639       break;
    640     case soclib::tlmt::VCI_LINKED_READ_COMMAND:
    641       {
    642 #if VCI_RAM_DEBUG
    643         std::cout << "[RAM " << m_tgtid << "] Receive from source " << srcid <<" a Locked Read packet "<< pktid << " Time = " << time.value() << std::endl;
    644 #endif
    645 
    646         vci_param::addr_t address;
    647         for (size_t i=0; i<nwords; i++){
    648           //if(payload.contig)
    649           address = (payload.get_address()+(i*vci_param::nbytes)) - s.baseAddress();//XXX contig = TRUE always
    650           //else
    651           //address = payload.get_address() - s.baseAddress();
    652 
    653           utoa(m_contents[segIndex][address / vci_param::nbytes], payload.get_data_ptr(),(i * vci_param::nbytes));
    654 
    655           //std::cout << "[RAM " << m_tgtid << "] LOCKED READ address = " << std::hex << (payload.get_address()+(i*vci_param::nbytes)) << " data  = " <<  m_contents[segIndex][address / vci_param::nbytes] << std::endl;
    656 
    657           m_atomic.doLoadLinked(address, srcid);
    658         }
    659 
    660         payload.set_response_status(tlm::TLM_OK_RESPONSE);
    661         phase = tlm::BEGIN_RESP;
    662         time = time + (nwords * UNIT_TIME);
    663 
    664 #if VCI_RAM_DEBUG
    665         std::cout << "[RAM " << m_tgtid << "] Send to source "<< srcid << " a anwser packet " << pktid << " Time = "  << time.value()  << std::endl;
    666 #endif
    667 
    668         p_vci_target->nb_transport_bw(payload, phase, time);
    669         return tlm::TLM_COMPLETED;
    670       }
    671       break;
    672     case soclib::tlmt::VCI_STORE_COND_COMMAND:
    673       {
    674 #if VCI_RAM_DEBUG
    675         std::cout << "[RAM " << m_tgtid << "] Receive from source " << srcid <<" a Store Conditionnel packet "<< pktid << " Time = "  << time.value() << std::endl;
    676 #endif
    677 
    678         vci_param::addr_t address;
    679         for (size_t i=0; i<nwords; i++){
    680           //if(payload.contig)
    681           address = (payload.get_address()+(i*vci_param::nbytes)) - s.baseAddress();//XXX contig = TRUE always
    682           //else
    683           //address = payload.get_address() - s.baseAddress();
    684 
    685           if(m_atomic.isAtomic(address, srcid)){
    686             m_atomic.accessDone(address);
    687 
    688             uint32_t index   = address / vci_param::nbytes;
    689             ram_t *tab       = m_contents[segIndex];
    690             unsigned int cur = tab[index];
    691             uint32_t mask    = atou(payload.get_byte_enable_ptr(), (i * vci_param::nbytes));
    692 
    693             tab[index] = (cur & ~mask) | (atou(payload.get_data_ptr(), (i * vci_param::nbytes)) & mask);
    694 
    695             //std::cout << "[RAM " << m_tgtid << "] STORE COND address = " << std::hex << (payload.get_address()+(i*vci_param::nbytes)) << " data  = " <<  tab[index] << std::endl;
    696 
    697             utoa(0, payload.get_data_ptr(),(i * vci_param::nbytes));
    698           }
    699           else{
    700             utoa(1, payload.get_data_ptr(),(i * vci_param::nbytes));
    701           }
    702         }
    703 
    704         payload.set_response_status(tlm::TLM_OK_RESPONSE);
    705         phase = tlm::BEGIN_RESP;
    706         time = time + (nwords * UNIT_TIME);
    707 
    708 #if VCI_RAM_DEBUG
    709         std::cout << "[RAM " << m_tgtid << "] Send to source "<< srcid << " a anwser packet " << pktid << " Time = "  << time.value()  << std::endl;
    710 #endif
    711 
    712         p_vci_target->nb_transport_bw(payload, phase, time);
    713         return tlm::TLM_COMPLETED;
    714       }
    715       break;
    716      default:
    717      break;
    718     }
     539    //set response status
     540    payload.set_response_status(tlm::TLM_OK_RESPONSE);
     541    //modify the phase
     542    phase = tlm::BEGIN_RESP;
     543    //increment the target processing time
     544    time = time + (nwords * UNIT_TIME);
     545    //send the response
     546    p_vci_target->nb_transport_bw(payload, phase, time);
     547    return tlm::TLM_COMPLETED;
     548    break;
     549  default:
     550    break;
    719551  }
    720552 
    721553  //send error message
    722554  payload.set_response_status(tlm::TLM_COMMAND_ERROR_RESPONSE);
    723  
     555  //modify the phase
    724556  phase = tlm::BEGIN_RESP;
     557  //increment the target processing time
    725558  time = time + nwords * UNIT_TIME;
    726  
    727 #if VCI_RAM_DEBUG
    728   std::cout << "[RAM " << m_tgtid << "] Address " << std::hex << payload.get_address() << std::dec << " does not match any segment " << std::endl;
    729   std::cout << "[RAM " << m_tgtid << "] Send to source "<< srcid << " a error packet with time = "  << time.value() << std::endl;
    730 #endif
     559  //send the response
    731560  p_vci_target->nb_transport_bw(payload, phase, time);
    732561  return tlm::TLM_COMPLETED;
    733562}
    734 
    735563
    736564}}}