Changes between Version 7 and Version 8 of Writing Rules/Tlmt

Timestamp:

Dec 25, 2007, 2:58:39 PM (16 years ago)

Author:

alain

Comment:

--

Writing Rules/Tlmt

@@ -43 +43 @@
 {{{
 class vci_cmd_t {
-vci_command_t  cmd;     // VCI transaction type
-vci_address_t  *address;  // pointer to an array of addresses on the target side
-uint32_t         *be;  // pointer to an array of byte_enable signals
+vci_param::vci_command_t  cmd;  // VCI transaction type
+vci_param::vci_address_t  *address;  // pointer to an array of addresses on the target side
+uint32_t  *be;  // pointer to an array of byte_enable signals
 bool   contig;    // contiguous addresses (when true) 
 vci_param::vci_data_t  *buf;  // pointer to the local buffer on the initiator 
-uint32_t         length;  // number of words in the packet
+uint32_t  length;  // number of words in the packet
 bool  eop;  // end of packet marker
 uint32_t  srcid;  // SRCID VCI
-uint32_t         trdid;  // TRDID VCI
-uint32_t         pktid;  // PKTID VCI
+uint32_t  trdid;  // TRDID VCI
+uint32_t  pktid;  // PKTID VCI
 }
 }}}
@@ -97 +97 @@
 A small value for this parameter result in a better timing accuracy for the simulation, but implies a larger number of context switch, and a slower simulation speed. 
 
-== C.4) TLM-T initiator example ==
+== C.4) VCI initiator example ==
 
 {{{
@@ -194 +194 @@
 }}}
   
-== D.4) TLM-T target example ==
+== D.4) VCI target example ==
  {{{
 template <typename vci_param>
@@ -239 +239 @@
 } // end class my_target
 }}}
+
+= E) Interconnection network modeling =
+
+= F) Interruption modeling =
+
+== F.1) Source modeling ==
+
+== F.2) Destination modeling ==
+
+== F.3)  processor with interrupt example ==
+
+class my_processor : Tlmt::BaseModule {
+public:
+    IrqInPort           p_irq;
+                
+    // constructor
+    my_processor (      sc_module_name  name,
+                uint32_t  lookahead) :
+    p_irq(“irq”, this, &my_initiator::irqReceived),
+    m_time(0),
+    BaseModule(name)
+    {
+    m_lookahed = lookahead;
+    m_counter = 0;
+    m_irqset = false;
+    SC_THREAD(execLoop);
+} // end constructor
+                
+private:
+    tlmt_Time  m_time;  // local clock 
+    bool  m_irqset;  // pending interrupt request
+    sc_time  m_irqtime;  // irq date
+    uint32_t  m_counter;  // iteration counter
+    uint32_t  m_lookahed;  // lookahead value
+
+    // thread 
+    void execLoop()
+    {
+    while(1) {
+        ...
+        // test interrupts
+        if (m_irqset && (m_irqtime <= m_time.getTime())) {
+                                        // traitement interrupt 
+                                        }
+                                ...
+        // lookahead management
+        m_counter++ ;
+        if (m_counter >= m_lookahead) {
+            m_counter = 0 ;
+            wait(SC_ZERO_TIME) ;
+            } // end if
+        m_time.addtime(1) ;
+        } // end while
+    } // end execLoop()
+
+// call-back function 
+     void  irqReceived(bool val, sc_time time) 
+    {
+    m_irqset = val;
+    m_irqtime = time;
+    } // end irqReceived()
+} // end class my_processor
+
+