Changes between Version 5 and Version 6 of Component/Mapping Table


Ignore:
Timestamp:
Jan 4, 2008, 1:05:00 PM (18 years ago)
Author:
Nicolas Pouillon
Comment:

More doc

Legend:

Unmodified
Added
Removed
Modified

  • Component/Mapping Table

    v5 v6  
    88
    99This object is basically an associative table, where each entry define a segment descriptor.
    10 A segment is a set of consecutive addresses in the address space. Each segment has a name, and is characterized by the following fields:
    11  * string '''name'''
    12  * addr_t '''base_address'''
    13  * size_t '''size'''
    14  * !IntTab '''target_index'''
    15  * bool '''cacheability'''
     10
     11The mapping table is a centralized description of both the address space segmentation,
     12and the mapping of the segments on the VCI physical targets.
     13
     14From this centralized description, it is possible to derive the '''routing tables''' used by the
     15hardware interconnect to decode the VCI address, and route the VCI packets to the proper target.
     16
     17All VCI initiators and VCI targets share the same  address space, but the address decoding
     18scheme can support a structured interconnect.
     19
     20= Usage =
     21
     22== Mapping Table ==
     23
     24Mapping table must know:
     25 * The address width
     26 * The number interconnection levels (most of the time 1 or 2)
     27 * The widths of the address subfields used for command routing
     28 * The widths of the RSRCID subfields used for response routing
     29 * The mask used in XCache for determining if an address is cacheable or not
     30
     31The number of interconnection levels is implicit by the length of lists of subfields lengths.
     32
     33MappingTable instanciation is:
     34
     35{{{
     36MappingTable maptab( addr_width, addr_bits, srcid_bits, cacheability_mask);
     37}}}
     38
     39For instance:
     40{{{
     41MappingTable maptab( 32, IntTab(8, 4), IntTab(8, 2), 0x000c0000);
     42}}}
     43
     44This creates a 32-bit MappingTable, with 2 level interconnection,
     458 address bits for global command routing, 4 address bits for local command routing,
     468 RSRCID bits for global response routing, 2 RSRCID bits for local response routing.
     47This makes RSRCID field 10-bit wide, this should be enforced.
     48
     49== Segments ==
     50
     51Segments holds information about a portion of addressable memory region, with some attributes:
     52 * a name
     53 * a base address
     54 * a size
     55 * a target_index (an !IntTab)
     56 * a cacheability flag
     57
    1658The size field is a number of bytes. The target_index field identifies the VCI target that contains
    1759the corresponding segment, and is used by the interconnect to route a command packet to the proper target.
    … …  
    2062All segments defined by the system designer for a given architecture must be non-overlaping.
    2163
    22 Therefore, the mapping table is a centralized description of both the address space segmentation,
    23 and the mapping of the segments on the VCI physical targets.
    24 From this centralized description, it is possible to derive the '''routing tables''' used by the
    25 hardware interconnect to decode the VCI address, and route the VCI packets to the proper target.
     64A Segment instanciation is:
     65{{{
     66Segment( name, base_address, size, target, cacheable )
     67}}}
    2668
    27 All VCI initiators and VCI targets share the same  address space, but the address decoding
    28 scheme can support a structured interconnect.
     69For instance:
     70{{{
     71Segment( "seg0", 0x50000, 0x1000, IntTab(3,2), true )
     72}}}
     73
     74This segment is associated to target on port 2 in cluster no 3. It is cacheable.
     75
     76It can be added in MappingTable with the method add():
     77{{{
     78maptab.add(Segment( "seg0", 0x50000, 0x1000, IntTab(3,2), true ))
     79}}}
     80
     81For each new segment added, the mapping table will ensure the segments are not overlapping.
     82
     83== Cacheability ==
     84
     85Cacheability is a by-segment attribute. It is associated to the address. Here, "seg0" is at address 0x50000, and cacheability mask is
     860xc0000, resulting cacheability-determining-address is `0x50000 & 0xc0000 = 0x40000`. Now, for any other address matching
     87`address & 0xc0000 = 0x40000`, cacheability will be true. This will be enforced by mapping_table or you'll get an `"Incoherent MappingTable" exception`.
     88
     89= Interconnection examples =
    2990
    3091== One level interconnect ==
    … …  
    3798   as the [wiki:Component/PibusBcu PibusBcu] or the [wiki:Component/VciVgmn VciVgmn] components)
    3899   make the assumption that the initiator indexes are between 0 and M -1 , where M is the total number of VCI initiators.
    39  * The VCI ADDRESS field is structured in two fields:  | MSB | OFFSET |
     100 * The VCI ADDRESS field is structured in two fields:  `| MSB | OFFSET |`
    40101   * The MSB field is decoded by the flat interconnect to route the command packet to the proper VCI target.
    41102   * The OFFSET field is decoded by the VCI target.
    … …  
    46107   0 and M -1 (where M is the total number of VCI initiators).
    47108
    48 Therefore, the flat interconnect must contain a ROM implementing a '''routing table''' indexed by the
    49 VCI ADDRESS MSB bits and containing the corresponding target index.
     109The flat interconnect must contain a ROM implementing a '''routing table''' indexed by the
     110VCI address MSBs and containing the corresponding target index.
    50111The content of this '''routing table''' is automatically computed by a method associated to the mapping table.
    51112
    52 == Two level interconnect ==
     113== Two-level interconnect ==
    53114
    54 With a two level interconnect, the hardware architecture is supposed to be split into several subsystems
     115With a two-level interconnect, the hardware architecture is supposed to be split into several subsystems
    55116(or clusters), with a global interconnect for inter-cluster communications, and one local interconnect in
    56117each cluster for intra-cluster communications.
    … …  
    59120   * a global index that identifies the subsystem (or cluster) index.
    60121   * a local index, that identifies the VCI component in the cluster.
    61  * all VCI targets in the same cluster must have the same global index.
    62  * all VCI targets in the same cluster must have different local indexes.
    63  * all VCI initiators in the same cluster must have the same global index.
    64  * all VCI initiators in the same cluster must have different local indexes.
    65  * The VCI ADDRESS field is structured in three fields : | MSB | LSB | OFFSET |
     122 * all VCI components in the same cluster must have the same global index.
     123 * all VCI components in the same cluster must have different local indexes.
     124 * The VCI ADDRESS field is structured in three fields : `| MSB | LSB | OFFSET |`
    66125   * The MSB field is decoded by the global interconnect to route the command packet to the proper cluster.
    67126   * The LSB field is decoded by the local interconnect to route the command packet to the proper target.
    68127   * The OFFSET field is decoded by the VCI target.
    69  * The VCI SRCID field is structured in two fields : | MSB | LSB |
     128 * The VCI SRCID field is structured in two fields : `| MSB | LSB |`
    70129   * The SRCID MSB field must be equal to the initiator global index.
    71130   * The SRCID LSB field must be equal to the initiator local index.
    … …  
    78137   have a different Local Routing Table.
    79138
     139== More levels ==
    80140
     141You may imagine those schemes are extensible to arbitrary level of interconnexion. The current !MappingTable, with
     142the help of `IntTab`s, is not limited.
     143