14 | | A '''chbuf descriptor''' is a circular array of '''buffer descriptors'''. |
15 | | Each buffer descriptor occupies 64 bytes, but only the first 8 bytes (64 bits) contain useful information: |
16 | | * The 48 LSB bits contain the buffer physical address |
17 | | * The MSB bit 63 defines the buffer state (empty if 0) |
18 | | The chbuf descriptor" base address must be a multiple of 64 bytes. |
| 14 | The state of each buffer must be defined in a variable called '''status'''. Each “status” occupies 64 bytes, but only the last bit is useful (1 if the buffer is full, 0 if it is empty). A buffer and its status physical addresses must be 64 bytes aligned and must have the same extension (identical bits[43:32]). |
| 15 | |
| 16 | A '''chbuf descriptor''' is a circular array of '''buffer descriptors'''. Each buffer descriptor occupies 64 bits: |
| 17 | * The 12 MSB bits contain the common extension of the buffer address and the buffer status address |
| 18 | * The 26 following bits contain the bits [31:6] of the buffer address |
| 19 | * The 26 LSB bits contain the bits [31:6] of the buffer status address |
| 20 | The "chbuf descriptor" base address must be a multiple of 64 bytes. |
27 | | The number of channels and the max burst length are constructor parameters: |
28 | | * The number of channels (simultaneous transfers) cannot be larger than 8. |
29 | | * The max burst length (in bytes) must be a power of 2 no larger than 64, and is typically equal to the system cache line width. If the source and/or destination buffers are not aligned on a burst boundary, the DMA controler split the burst in two VCI transactions. |
| 29 | The transfer between a SRC and a DST buffer is divided into several bursts, and more precisely into series of several pipelined bursts. In a series of pipelined bursts, all the read requests are sent successively and the responses are stored in a local fifo (one fifo per channel). Then the successive write commands are sent to the DST buffer. |
| 30 | |
| 31 | The number of channels, the max burst length and the number of stages in the pipeline are constructor parameters: |
| 32 | * The number of channels (simultaneous transfers) cannot be larger than 8. |
| 33 | * The max burst length (in bytes) must be a power of 2 no larger than 64, and is typically equal to the system cache line width. |
| 34 | * The number of pipelined bursts cannot be larger than 4 (default parameter). |
| 35 | |
| 36 | The total storage capacity for transferred data is channels * pipelined_bursts * burst_max_length. |
49 | | || Channel Status || value || || |
50 | | || CHANNEL_IDLE || 0 || channel not running || |
51 | | || CHANNEL_SRC_DESC_ERROR || 1 || bus error accessing SRC CHBUF descriptor || |
52 | | || CHANNEL_DST_DESC_ERROR || 2 || bus error accessing DST CHBUF descriptor || |
53 | | || CHANNEL_SRC_DATA_ERROR || 3 || bus error accessing SRC CHBUF data || |
54 | | || CHANNEL_DST_DATA_ERROR || 4 || bus error accessing DST CHBUF data || |
55 | | || CHANNEL_BUSY || >4 || channel running || |
| 56 | || Channel Status || value || || |
| 57 | || CHANNEL_IDLE || 0 || channel not running || |
| 58 | || CHANNEL_SRC_DESC_ERROR || 1 || bus error accessing SRC CHBUF descriptor || |
| 59 | || CHANNEL_DST_DESC_ERROR || 2 || bus error accessing DST CHBUF descriptor || |
| 60 | || CHANNEL_SRC_STATUS_ERROR || 3 || bus error accessing SRC BUF status || |
| 61 | || CHANNEL_DST_STATUS_ERROR || 4 || bus error accessing SRC BUF status || |
| 62 | || CHANNEL_DATA_ERROR || 5 || bus error accessing SRC or DST CHBUF data || |
| 63 | || CHANNEL_BUSY || >5 || channel running || |
83 | | const soclib::common::IntTab &srcid, // Initiator index |
84 | | const soclib::common::IntTab &tgtid, // Target index |
85 | | const size_t burst_max_length, // Max number of bytes transfered in a burst |
86 | | const size_t channels ); // Number of channels |
| 91 | const soclib::common::IntTab &srcid, // Initiator index |
| 92 | const soclib::common::IntTab &tgtid, // Target index |
| 93 | const uint32_t burst_max_length, // Max number of bytes transferred in a burst |
| 94 | const uint32_t channels, // Number of channels |
| 95 | const uint32_t pipelined_bursts ); // Number of pipelined bursts |