7 | | The active state is high, and the output interrupt '''p_irq''' is the logical OR of all |
8 | | input interrupts '''p_irq_in[i]'''. |
9 | | Each input interrupt '''p_irq_in[i]''' can be individually masked |
10 | | using a memory mapped 32 bits register . |
11 | | This component can return the index of the highest priority |
| 7 | The active state is high, and the output interrupt is the logical OR of all |
| 8 | input interrupts. |
| 9 | Each input interrupt can be individually masked |
| 10 | using a memory mapped 32 bits register. |
| 11 | This component can be addresse to return the index of the highest priority |