Changes between Version 1 and Version 2 of Component/Vci Xcache
- Timestamp:
- May 17, 2007, 11:09:31 AM (17 years ago)
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Component/Vci Xcache
v1 v2 31 31 32 32 == Data Cache == 33 33 34 * The Data cache is direct mapping, and the write policy is WRITE-THROUGH (the data is immediately written in memory, and the cache is updated only in case of HIT). 34 * The data cache contains a 8 wordswrite buffer. The cache controller builds a burst packet when there is several successive write addresses in the write buffer for the same 4 Kbytes page.35 * The data cache contains a parametrably-sized write buffer. The cache controller builds a burst packet when there is several successive write addresses in the write buffer for the same 4 Kbytes page. 35 36 * It uses the [wiki:Component/MappingTable Mapping Table] to support uncached segments. 36 37 * The Data cache accepts a line invalidate command. … … 50 51 == Template parameters == 51 52 52 template<typename vci_param> 53 {{{ 54 template<size_t write_buffer_depth, typename vci_param> 55 }}} 56 57 Standard size for write buffer is 8 words. 53 58 54 59 == Constructor parameters == 55 60 {{{ 56 VciXcache( 57 sc_module_name name, // Instance name58 const soclib::common::MappingTable &mt, // Mapping Table59 const soclib::common::IntTab &index, // VCI Initiator index60 size_t WRITE_BUFFER_DEPTH, // number of requests in the write buffer61 size_t ICACHE_LINES, // number of lines for the Icache62 size_t ICACHE_WORDS, // number of words per line for the Icache63 size_t DCACHE_LINES, // number of lines for the Dcache64 size_t DCACHE_WORDS); // number or words per line for the Dcache61 62 VciXCache( 63 sc_module_name insname, 64 const soclib::common::MappingTable &mt, 65 const soclib::common::IntTab &index, 66 size_t icache_lines, 67 size_t icache_words, 68 size_t dcache_lines, 69 size_t dcache_words ); 65 70 }}} 66 71