Changes between Version 20 and Version 21 of Component/Vci Xcache Wrapper

Timestamp:

Sep 16, 2009, 11:49:12 AM (16 years ago)

Author:

alain

Comment:

--

Component/Vci Xcache Wrapper

@@ -62 +62 @@
 This MMU performs both the logical address to physical address translation, and access rights checking.
  * The logical address is 32 bits.
- * The Physical address is 36 bits (or less).
+ * The Physical address is 40 bits (or less).
  * It is implemented as a two level, hierarchical, page table. 
- * Both first & second level page table contains 1024 entries. 
  * Two page sizes are supported : 4 Kbytes, or 4 Mbytes.
  * Separated TLBs are used for instruction and data addresses.
- * Separated TLBS are used for 4 Kbytes and 4 Mbytes pages (accessed in parallel).
  * The TLB misses are handled by hardware (hardwired table-walk).
- * An execution context is defined by the value stored in the PTPR (Page Table Pointer Register). 
- * Any context switch flush both the instruction & data TLBs.
-
-The page page descriptor format is 32 bits:
-
-||ET ||  Entry Type                                            || 2 bits  ||
-||C   || Cachable                                               || 1 bit    ||
-||W  || Writable                                                 || 1 bit    ||
-||X   || eXecutable                                            || 1 bit    ||
-||U   || User 'access in user mode allowed  || 1 bit    ||
-||G   || Global (not invalidate by TLB flush  || 1 bit    ||
-||D   || Dirty  (page has been modified)       || 1 bit    ||
-||PPN||Physical Page Number                        || 24 bits ||
-
-The generic MMU defines 10 registers, that can be accessed by the software through the generic cache/proccessor interface defined in source:root/trunk/soclib/soclib/lib/iss2/include/iss2.h
-
-|| PTPR                   || set Page Table Pointer Register        || Write ||
-|| TLB_EN               || set Data & Inst TLBs Mode Register  || Write || 
-|| ICACHE_FLUSH  || Instruction Cache flush                     || Write ||
-|| DCACHE_FLUSH || Data Cache flush                                || Write ||
-|| ITLB_INVAL         || Instruction TLB line invalidate          || Write ||
-|| DTLB_INVAL       || Data TLB line invalidate                     || Write ||
-|| ICACHE_INVAL  || Instruction Cache line invalidate       || Write ||
-|| DCACHE_INVAL || Data Cache line invalidate                 || Write ||
-|| BAD_VADDR      || Bad Virtual Address Register             || Read ||
-|| ERR_TYPE           || Exception type Register                      || Read ||
-
-Both the instruction & data caches are accessed with physical addresses.
-
-In the Vcache and CC_Vcache components, the cachability (for both instruction & data accesses) can be defined 
-by software - on a per-logical-page basis) through the cacheability attribut contained in each page descriptor.
-But the cachability can also be controlled (on a per-physical-segment basis) through the mapping table.
+ 
+A more detailed specification of the generic MMU can be find on the Web site of the TSAR project :
+[https://www-asim.lip6.fr/trac/tsar/wiki/VirtualMemory]
   
 === Cache Coherence ===