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= What is SoCLib =

 * SoCLib is an open platform for virtual prototyping of multi-processors system on chip (MP-SoC).
 * The project started as an ANR-founded project. It is now maintained at [http://www.lip6.fr/ Lip6]

 * The core of the platform is a library of SystemC simulation models for virtual components (IP cores)
 * The main concern is true interoperability between the SoCLib IP cores
 * All simulation models are written in SystemC, and can be simulated with the standard SystemC simulation environment.
 * Two types of models are available for each IP-core:
  * CABA (Cycle Accurate / Bit Accurate),
  * TLM-DT (Transaction Level Modeling with Distributed Time)
 * All [wiki:Component simulation models] and most associated tools are distributed as free software.

= Using SoCLib =

== SoCLib Components ==

 * [wiki:Component SoCLib Components General Index] : documentation about the available hardware components (IP cores) 

==  Installation ==

 * If you want to try SoCLib without going through the installation process, the [https://www.soclib.fr/appliance/ SoCLib Virtual machine appliance] may help you !
 * [wiki:InstallationNotes Installation Notes] : how to install the SoCLib platform on your computer
 * [wiki:FrequentlyAskedQuestions Frequently asked questions] is useful when things goes wrong

== Documentation ==

 * [wiki:Component SoCLib Components Index]
 * [http://www.soclib.fr/doc/ Tools dedicated documentation]
 * [http://www.soclib.fr/doc/soclib-cc/ soclib-cc command line tool help]
 * [http://www.soclib.fr/doc/sd-file/ metadata (`.sd`) file format]
 * [http://www.soclib.fr/doc/configuration/ configuration file format]
 * [http://www.soclib.fr/doc/build/ description of the build process]
 * [wiki:SoclibCc/AndModelsim Usage of Soclib-cc with modelsim for mixed SystemC / VHDL cosimulation]

= Projects using SoCLib =

 * [https://www-soc.lip6.fr/trac/tsar/ TSAR, Tera-Scale Architecture]: a scalable, shared-memory, coherent MP2-SoC

= Software support =

== Embedded Os support ==

SoCLib platforms are able to run several operating systems:
 * [wiki:Tools/Muteka DNA/OS] : DNA/OS is a micro-kernel for MPSoCs. It supersedes MutekA, and still provides the POSIX thread API. 
 * [http://www.mutekh.org/ MutekH] : Exo-kernel based OS for classical and heterogeneous MPSoCs with POSIX threads support
 * [http://www.netbsd.org/ NetBSD] : Highly portable Unix-like Open Source operating system
 * [http://ecos.sourceware.org/ eCos] : An open source, royalty-free, real-time operating system intended for embedded applications.
 * [http://www.rtems.com/ RTEMS] : Real-Time Operating System for Multiprocessor Systems

== SoCLib Tools ==

Various tools comes along with SoCLib to ease research and development:
 * [wiki:Tools/Dsx DSX] : Design Space Exploration tool
 * [wiki:Tools/SystemCass SystemCASS] : Fast SystemC simulation kernel
 * [wiki:Tools/SocView SoCView] : Interactive simulation environment for debug and instrumentation
 * [wiki:Tools/GdbServer GdbServer] : A GDB server for multi-processor architectures
 * [wiki:Tools/MemoryChecker MemoryChecker] : A memory access error checker similar to valgrind.
 * [wiki:Tools/GAUT GAUT] : A high-level synthesis tool allowing to generate automatically systemC CABA and TLM-T files.

== Middleware ==

 * [wiki:Tools/Mwmr MWMR] : Hardware / Software communication middleware

== Tutorials ==

 * [https://www-asim.lip6.fr/trac/dsx/wiki/MjpegCourse DSX tutorial]: Motion-JPEG, MWMR, MutekH, DSX, Design-space exploration
 * [wiki:Motion-JPEG DNA Motion-JPEG and OS tutorial]

= Development =

==  Writing and design guides ==

 * [wiki:WritingRules/General General SoCLib Rules] : general rules regarding the SoCLib components.
 * [wiki:WritingRules/RISC Processor Modeling] : a general method to write generic processor models.
 * [wiki:WritingRules/Caba CABA Writing Rules] : rules to write SystemC CABA simulation models.
 * [wiki:WritingRules/Tlmt TLM-DT Writing Rules] : rules to write SystemC TLM-DT simulation models.
 * [wiki:WritingRules/TLMT Critères Pour Plate-Forme TLM-T] : criteria defined for writing TLM-T simulation models.
 * [wiki:WritingRules/Transactors CABA/TLM-DT Transactors] : general principles

 * [wiki:AddComponent Adding new components to the library] : the rules to follow to add a new IP core to the library.
 * VciProtocol : VCI protocol considerations in SoCLib

= SoCLib Resources =

== Publications ==

See PapersAndPublications.

== Mailing list ==

The [mailto:dev@soclib.fr] Mailing list is public and targets general discussion about SoCLib component development.

To join the list, either
 * send an email to `dev-subscribe@soclib.fr`;
 * see [http://www.soclib.fr/wws/info/dev].