570 | | switch(extension_pointer->get_command()){ |
571 | | case soclib::tlmt::VCI_READ_COMMAND: |
572 | | { |
573 | | #if VCI_RAM_DEBUG |
574 | | std::cout << "[RAM " << m_tgtid << "] Receive from source "<< srcid << " a read packet " << pktid << " Time = " << time.value() << std::endl; |
575 | | #endif |
576 | | |
577 | | vci_param::addr_t address; |
578 | | for (size_t i=0;i<nwords;i++){ |
579 | | //if (payload.contig) |
580 | | address = (payload.get_address()+(i*vci_param::nbytes)) - s.baseAddress(); //XXX contig = TRUE always |
581 | | //else |
582 | | //address = payload.get_address() - s.baseAddress(); //always the same address |
583 | | |
584 | | utoa(m_contents[segIndex][address / vci_param::nbytes], payload.get_data_ptr(),(i * vci_param::nbytes)); |
585 | | |
586 | | //std::cout << "[RAM " << m_tgtid << "] READ address = " << std::hex << (payload.get_address()+(i*vci_param::nbytes)) << " data = " << m_contents[segIndex][address / vci_param::nbytes] << std::endl; |
587 | | |
588 | | } |
589 | | |
590 | | payload.set_response_status(tlm::TLM_OK_RESPONSE); |
591 | | phase = tlm::BEGIN_RESP; |
592 | | time = time + (nwords * UNIT_TIME); |
593 | | |
594 | | #if VCI_RAM_DEBUG |
595 | | std::cout << "[RAM " << m_tgtid << "] Send to source "<< srcid << " a anwser packet " << pktid << " Time = " << time.value() << std::endl; |
596 | | #endif |
597 | | |
598 | | p_vci_target->nb_transport_bw(payload, phase, time); |
599 | | return tlm::TLM_COMPLETED; |
600 | | } |
601 | | break; |
602 | | case soclib::tlmt::VCI_WRITE_COMMAND: |
603 | | { |
604 | | #if VCI_RAM_DEBUG |
605 | | std::cout << "[RAM " << m_tgtid << "] Receive from source " << srcid <<" a Write packet "<< pktid << " Time = " << time.value() << std::endl; |
606 | | #endif |
607 | | |
608 | | vci_param::addr_t address; |
609 | | for (size_t i=0; i<nwords; i++){ |
610 | | //if(payload.contig) |
611 | | address = (payload.get_address()+(i*vci_param::nbytes)) - s.baseAddress();//XXX contig = TRUE always |
612 | | //else |
613 | | //address = payload.get_address() - s.baseAddress(); |
614 | | |
615 | | m_atomic.accessDone(address); |
616 | | |
617 | | uint32_t index = address / vci_param::nbytes; |
618 | | ram_t *tab = m_contents[segIndex]; |
619 | | unsigned int cur = tab[index]; |
620 | | uint32_t mask = atou(payload.get_byte_enable_ptr(), (i * vci_param::nbytes)); |
621 | | |
622 | | tab[index] = (cur & ~mask) | (atou( payload.get_data_ptr(), (i * vci_param::nbytes) ) & mask); |
623 | | |
624 | | //std::cout << "[RAM " << m_tgtid << "] WRITE address = " << std::hex << (payload.get_address()+(i*vci_param::nbytes)) << " data = " << tab[index] << std::endl; |
625 | | |
626 | | } |
627 | | |
628 | | payload.set_response_status(tlm::TLM_OK_RESPONSE); |
629 | | phase = tlm::BEGIN_RESP; |
630 | | time = time + (nwords * UNIT_TIME); |
631 | | |
632 | | #if VCI_RAM_DEBUG |
633 | | std::cout << "[RAM " << m_tgtid << "] Send to source "<< srcid << " a anwser packet " << pktid << " Time = " << time.value() << std::endl; |
634 | | #endif |
635 | | |
636 | | p_vci_target->nb_transport_bw(payload, phase, time); |
637 | | return tlm::TLM_COMPLETED; |
638 | | } |
639 | | break; |
640 | | case soclib::tlmt::VCI_LINKED_READ_COMMAND: |
641 | | { |
642 | | #if VCI_RAM_DEBUG |
643 | | std::cout << "[RAM " << m_tgtid << "] Receive from source " << srcid <<" a Locked Read packet "<< pktid << " Time = " << time.value() << std::endl; |
644 | | #endif |
645 | | |
646 | | vci_param::addr_t address; |
647 | | for (size_t i=0; i<nwords; i++){ |
648 | | //if(payload.contig) |
649 | | address = (payload.get_address()+(i*vci_param::nbytes)) - s.baseAddress();//XXX contig = TRUE always |
650 | | //else |
651 | | //address = payload.get_address() - s.baseAddress(); |
652 | | |
653 | | utoa(m_contents[segIndex][address / vci_param::nbytes], payload.get_data_ptr(),(i * vci_param::nbytes)); |
654 | | |
655 | | //std::cout << "[RAM " << m_tgtid << "] LOCKED READ address = " << std::hex << (payload.get_address()+(i*vci_param::nbytes)) << " data = " << m_contents[segIndex][address / vci_param::nbytes] << std::endl; |
656 | | |
657 | | m_atomic.doLoadLinked(address, srcid); |
658 | | } |
659 | | |
660 | | payload.set_response_status(tlm::TLM_OK_RESPONSE); |
661 | | phase = tlm::BEGIN_RESP; |
662 | | time = time + (nwords * UNIT_TIME); |
663 | | |
664 | | #if VCI_RAM_DEBUG |
665 | | std::cout << "[RAM " << m_tgtid << "] Send to source "<< srcid << " a anwser packet " << pktid << " Time = " << time.value() << std::endl; |
666 | | #endif |
667 | | |
668 | | p_vci_target->nb_transport_bw(payload, phase, time); |
669 | | return tlm::TLM_COMPLETED; |
670 | | } |
671 | | break; |
672 | | case soclib::tlmt::VCI_STORE_COND_COMMAND: |
673 | | { |
674 | | #if VCI_RAM_DEBUG |
675 | | std::cout << "[RAM " << m_tgtid << "] Receive from source " << srcid <<" a Store Conditionnel packet "<< pktid << " Time = " << time.value() << std::endl; |
676 | | #endif |
677 | | |
678 | | vci_param::addr_t address; |
679 | | for (size_t i=0; i<nwords; i++){ |
680 | | //if(payload.contig) |
681 | | address = (payload.get_address()+(i*vci_param::nbytes)) - s.baseAddress();//XXX contig = TRUE always |
682 | | //else |
683 | | //address = payload.get_address() - s.baseAddress(); |
684 | | |
685 | | if(m_atomic.isAtomic(address, srcid)){ |
686 | | m_atomic.accessDone(address); |
687 | | |
688 | | uint32_t index = address / vci_param::nbytes; |
689 | | ram_t *tab = m_contents[segIndex]; |
690 | | unsigned int cur = tab[index]; |
691 | | uint32_t mask = atou(payload.get_byte_enable_ptr(), (i * vci_param::nbytes)); |
692 | | |
693 | | tab[index] = (cur & ~mask) | (atou(payload.get_data_ptr(), (i * vci_param::nbytes)) & mask); |
694 | | |
695 | | //std::cout << "[RAM " << m_tgtid << "] STORE COND address = " << std::hex << (payload.get_address()+(i*vci_param::nbytes)) << " data = " << tab[index] << std::endl; |
696 | | |
697 | | utoa(0, payload.get_data_ptr(),(i * vci_param::nbytes)); |
698 | | } |
699 | | else{ |
700 | | utoa(1, payload.get_data_ptr(),(i * vci_param::nbytes)); |
701 | | } |
702 | | } |
703 | | |
704 | | payload.set_response_status(tlm::TLM_OK_RESPONSE); |
705 | | phase = tlm::BEGIN_RESP; |
706 | | time = time + (nwords * UNIT_TIME); |
707 | | |
708 | | #if VCI_RAM_DEBUG |
709 | | std::cout << "[RAM " << m_tgtid << "] Send to source "<< srcid << " a anwser packet " << pktid << " Time = " << time.value() << std::endl; |
710 | | #endif |
711 | | |
712 | | p_vci_target->nb_transport_bw(payload, phase, time); |
713 | | return tlm::TLM_COMPLETED; |
714 | | } |
715 | | break; |
716 | | default: |
717 | | break; |
718 | | } |
| 539 | //set response status |
| 540 | payload.set_response_status(tlm::TLM_OK_RESPONSE); |
| 541 | //modify the phase |
| 542 | phase = tlm::BEGIN_RESP; |
| 543 | //increment the target processing time |
| 544 | time = time + (nwords * UNIT_TIME); |
| 545 | //send the response |
| 546 | p_vci_target->nb_transport_bw(payload, phase, time); |
| 547 | return tlm::TLM_COMPLETED; |
| 548 | break; |
| 549 | default: |
| 550 | break; |