| 1 | /*
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| 2 | *
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| 3 | * SOCLIB_LGPL_HEADER_BEGIN
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| 4 | *
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| 5 | * This file is part of SoCLib, GNU LGPLv2.1.
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| 6 | *
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| 7 | * SoCLib is free software; you can redistribute it and/or modify it
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| 8 | * under the terms of the GNU Lesser General Public License as published
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| 9 | * by the Free Software Foundation; version 2.1 of the License.
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| 10 | *
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| 11 | * SoCLib is distributed in the hope that it will be useful, but
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| 12 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 14 | * Lesser General Public License for more details.
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| 15 | *
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| 16 | * You should have received a copy of the GNU Lesser General Public
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| 17 | * License along with SoCLib; if not, write to the Free Software
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| 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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| 19 | * 02110-1301 USA
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| 20 | *
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| 21 | * SOCLIB_LGPL_HEADER_END
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| 22 | *
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| 23 | * Copyright (c) UPMC, Lip6, SoC
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| 24 | * Nicolas Pouillon <nipo@ssji.net>, 2006-2007
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| 25 | *
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| 26 | * Maintainers: nipo
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| 27 | */
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| 28 |
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| 29 | /////////////////////////////////////////////////////////////////
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| 30 | // ADDRESS SPACE SEGMENTATION
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| 31 | //
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| 32 | // This file must be included in the system.cpp file,
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| 33 | // for harware configuration : It is used to build
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| 34 | // the SOCLIB_SEGMENT_TABLE.
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| 35 | //
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| 36 | // This file is also used by the ldscript generator,
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| 37 | // for embedded software generation.
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| 38 | //
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| 39 | // It gives the system integrator the garanty
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| 40 | // that hardware and software have the same
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| 41 | // description of the address space segmentation.
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| 42 | //
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| 43 | // The segment names cannot be changed.
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| 44 | /////////////////////////////////////////////////////////////////
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| 45 |
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| 46 | /////////////////////////////////////////////////////////////////
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| 47 | // text, reset, and exception segments
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| 48 | /////////////////////////////////////////////////////////////////
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| 49 |
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| 50 | #define MEMORY_BASE 0x10000000
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| 51 | #define MEMORY_SIZE 0x01000000
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| 52 | #define MEMORY_BASE1 0x20000000
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| 53 | #define MEMORY_SIZE1 0x01000000
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| 54 |
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| 55 |
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| 56 |
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| 57 | /* base address required by MIPS processor */
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| 58 | #define RESET_BASE 0xBFC00000
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| 59 | #define RESET_SIZE 0x00010000
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| 60 |
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| 61 | /* base address required by MIPS processor */
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| 62 | #define EXCEP_BASE 0x80000000
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| 63 | #define EXCEP_SIZE 0x00010000
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| 64 |
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| 65 |
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| 66 |
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| 67 |
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| 68 |
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| 69 | /* channel memory */
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| 70 | #define CHANNEL_MEMORY_BASE 0xB0200000
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| 71 | #define CHANNEL_MEMORY_SIZE 0x00010000
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| 72 |
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| 73 |
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| 74 | //////////////////////////////////////////////////////////
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| 75 | // System devices
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| 76 | ///////////////////////////////////////////////////////////
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| 77 |
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| 78 | #define TTY_BASE 0xC0000000
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| 79 | #define TTY_SIZE 0x00000040
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| 80 |
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| 81 | #define TIMER_BASE 0xC1000000
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| 82 | #define TIMER_SIZE 0x00000100
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| 83 |
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| 84 | #define LOCKS_BASE 0xC2000000
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| 85 | #define LOCKS_SIZE 0x00000400
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| 86 |
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| 87 |
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| 88 | #define DMA_BASE 0xD0200000
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| 89 | #define DMA_SIZE 0x00001000
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| 90 |
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| 91 | #define FB_BASE 0xF0200000
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| 92 | #define FB_SIZE 0x00100000
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| 93 |
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| 94 | #define FD_BASE 0xE0200000
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| 95 | #define FD_SIZE 0x00000100
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| 96 |
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| 97 |
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