Multi-processor platform with several loaders

[alexandre.chagoya-garzon@…]

Hi, I am trying to write a multi-processor platform with private program memories, and I was trying to figure out if this was possible with SOCLIB. I made a try with 2 Mips in a first phase, with two associated mapping tables. The difference between both mappings is the MEMORY address, 0x10000000 for Mips0 and 0x20000000 for Mips1. I created two loaders taking different binaries, the reset section of the first jumps to 0x10xxxx and the second jumps to 0x20xxx.

Loader loader0("MJPEG0.x");

VciRam<vci_param> vcimultiram0("vcimultiram0", IntTab(0,0), maptab, loader0);

Loader loader1("MJPEG1.x");

VciRam<vci_param> vcimultiram1("vcimultiram1", IntTab(1,0), maptab1, loader1);

MJPEG0.x:

211735 bfc00020: 3c1b1001 lui k1,0x1001

211736 bfc00024: 277bf360 addiu k1,k1,-3232

MJPEG1.x:

202290 bfc00020: 3c1b2001 lui k1,0x2001

202291 bfc00024: 277bb820 addiu k1,k1,-18400

However, when I execute the simulation, I see that cache1 seems to execute the reset section of MJPEG0.x.

cache0 PC: 0xbfc00020 NPC: 0xbfc00024 Ins: 0x3c1b1001

cache0 PC: 0xbfc00024 NPC: 0xbfc00028 Ins: 0x277bf360

cache1 PC: 0xbfc00020 NPC: 0xbfc00024 Ins: 0x3c1b1001

cache1 PC: 0xbfc00024 NPC: 0xbfc00028 Ins: 0x277bf360

Did I do something wrong?

Thank you Alexandre

[Nicolas Pouillon]

Your approach is good, but you are not altering the Mapping Table for the right components. I've got two solutions for you:

First

Mapping Table serves 3 goals:

• Inform the targets of the semgents attributed to them
• Inform the initiators of their srcid, and cacheability masks
• Inform the routing components (vgmn, crossbar, ...) of the routing tables.

Here, you are trying to make the routing different for these two paths:

• cpu0 -> 0xbfc00000
• cpu1 -> 0xbfc00000

So you must have two paths from each CPU to their rams, going through at least 1 different interconnect.

Therefore, you need a clustered architecture with:

• A global interconnect
• Two crossbars
• A CPU on each crossbar
• A RAM on each crossbar
• Two mapping tables (the ones you created are fine) attached each to a cluster (crossbar+ram+CPU)
• Attaching any one of the two mapping tables to the VGMN should be fine.

Second

Now, from the code I see, you seem to only want to change the boot code (read-only) depending on the initiator. For this task, there is a VciHeterogeneousRom component, which is a component designed to answer from a different Loader depending on the srcid requesting data. This could fit your needs, without creating a clustered architecture (which is a bit of an overkill).

[alexandre.chagoya-garzon@…]

Thanks for the help! I will try the second solution also, however I had followed the first approach as I wrote this ticket (the only difference is that I used a dspin on which are connected the two clusters and other components, and not a VGMN). This time I am pretty sure of the IDs I used :D, could you tell me if this is a bug or if I again blundered on the ids? :)

Best regards Alexandre

[Nicolas Pouillon]

About the ids, I dont know, I cant tell without actual netlist...

Hearing no news, I'm assuming this is solved. Reopen the ticket if needed.