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Ticket Resolution Summary Owner Reporter
#41 fixed Binding error with cache coherence on sparcv8 ISS developers fabien.colas-bigey@…
Description

The platform is based on the topcell example : caba-ring-ccxcachev1_memcachev1-mipsel. Here are the main differences:

  • Sparcv8 instead of mipsel32
  • Different memory segments
  • No MMU define in the segmentation.h file
  • Different linker script for soft (in order to meet sparcv8 requirements)
  • Only 4 irqs instead of 5 (sparcv8 requirement)

The problem is that the platform compiles but there is a binding error when launching the system.

Error: (E109) complete binding failed: 2 binds exceeds maximum of 1 allowed: port 'proc3.vci_ini_rw_rspack' (sc_out)

I checked all connexions and it seems ok for me. If anyone could help, this would be great.

Many thanks, Fabien.

#35 fixed Bug in the Sparc V8 component (LDA instruction) developers quentin.meunier@…
Description

While trying to run a sample code on the sparc processor, an error arised : line 80, the test

if(ins.format3a.i == 0) {                                       \
            m_exception = true;                                         \
            m_exception_cause = TP_ILLEGAL_INSTRUCTION;

is actually the contrary :

if(ins.format3a.i == 1) {                                       \
            m_exception = true;                                         \
            m_exception_cause = TP_ILLEGAL_INSTRUCTION;

cf. the sparc V8 reference manual, p. 160 (163), test on code line 9.

#1 duplicate Can i see the SoCLib? somebody Qiang Wang <wq_make@…>
Description

hi,My name is Qiang Wang.I am a graduate student. Can i see the source of SoCLib? If i can't,please tell me why.thanks

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