#41 closed helpdesk (fixed)
Binding error with cache coherence on sparcv8 ISS
| Reported by: | Owned by: | developers | |
|---|---|---|---|
| Priority: | N/A | Component: | IP-Cores |
| Keywords: | Cc: |
Description
The platform is based on the topcell example : caba-ring-ccxcachev1_memcachev1-mipsel. Here are the main differences:
- Sparcv8 instead of mipsel32
- Different memory segments
- No MMU define in the segmentation.h file
- Different linker script for soft (in order to meet sparcv8 requirements)
- Only 4 irqs instead of 5 (sparcv8 requirement)
The problem is that the platform compiles but there is a binding error when launching the system.
Error: (E109) complete binding failed: 2 binds exceeds maximum of 1 allowed: port 'proc3.vci_ini_rw_rspack' (sc_out)
I checked all connexions and it seems ok for me. If anyone could help, this would be great.
Many thanks, Fabien.
Attachments (2)
Change History (4)
Changed 16 years ago by
| Attachment: | caba-ring-ccxcachev1_memcachev1-sparcv8.tgz added |
|---|
comment:1 Changed 16 years ago by
| Resolution: | → fixed |
|---|---|
| Status: | new → closed |
There are only 4 IRQs on sparc, therefore, you must use IRQ lines 0 to 3 (not 0 to 4). In the attached topcell, you dereference caches's p_irq[4], which aliases what follows in memory (by chance, another port), and you get the error above.
Please see topcell.diff for a fix.
comment:2 Changed 16 years ago by
| Priority: | major → N/A |
|---|---|
| Type: | defect → helpdesk |


Complete platform : requires sparcv8 elf compiler