Opened 14 years ago

Closed 14 years ago

Last modified 14 years ago

#36 closed defect (invalid)

[MIPS32] sync does not flush read operation as it is supposed to

Reported by: xavier.guerin@… Owned by: developers
Priority: major Component: IP-Cores
Keywords: MIPS32 CACHE SYNC Cc:

Description

When sync is called on Mips32, only pending write operation are flushed, and not the pending read operation, as they are supposed to.

Change History (3)

comment:1 Changed 14 years ago by Nicolas Pouillon

If the sync request gets to the cache, then it is a cache issue. What is your cache model ?

comment:2 Changed 14 years ago by xavier.guerin@…

Resolution: → invalid
Status: new → closed

I carefully read the documentation of the Mips32, and sync is NOT supposed to flush the cache, only guarantee that read operation are performed (the target register has been updated) and the write operations are commited. I'm an idiot.

I just need to find a way to send DCACHE_INVALIDATE to the cache, probably through cp0. Sorry to bother.

comment:3 Changed 14 years ago by Nicolas Pouillon

See cache instruction.

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