| | 1 | [wiki:Component SocLib Components General Index] |
| | 2 | |
| | 3 | = !DspinRouter = |
| | 4 | |
| | 5 | == Functional Description == |
| | 6 | |
| | 7 | This hardware component is the generic router for the DSPIN micronetwork. It can be used in conjunction with the [wiki:Component/VciDspinTargetWrapper VciDspinTargetWrapper] and the [wiki:Component/VciDspinInitiatorWrapper VciDspinInitiatorWrapper] components to build a VCI compliant DSPIN micro-network. It implements a packet switching network, with a wormhole |
| | 8 | routing strategy, for low latency. |
| | 9 | |
| | 10 | The DSPIN network on chip is a distributed network, with a 2D mesh topology. It has been designed for shared memory clusterized, |
| | 11 | multi-processors architectures. It supports the GALS (Globally Asynchronous Locally Synchronous) approach. |
| | 12 | |
| | 13 | == Component definition == |
| | 14 | |
| | 15 | == Usage == |
| | 16 | |
| | 17 | == CABA Implementation == |
| | 18 | |
| | 19 | * interface : source:trunk/soclib/soclib/module/network_component/vci_dspin_initiator_wrapper/caba/source/include/dspin_router.h |
| | 20 | * implementation : source:trunk/soclib/soclib/module/network_component/vci_dspin_initiator_wrapper/caba/source/src/dspin_router.cc |
| | 21 | |
| | 22 | == TLM-T implementation == |
| | 23 | |
| | 24 | There is no TLM-T implementation for the DSPIN network. |
| | 25 | (You can use the VciVgmn generic interconnect) |
| | 26 | |
| | 27 | == Template parameters == |
| | 28 | |
| | 29 | == Constructor parameters == |
| | 30 | |
| | 31 | == Ports == |
| | 32 | |
