Changes between Version 4 and Version 5 of Component/Mips32


Ignore:
Timestamp:
Dec 9, 2009, 10:09:44 AM (14 years ago)
Author:
Nicolas Pouillon
Comment:

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  • Component/Mips32

    v4 v5  
    99
    1010It implements all instructions defined in the MIPS32 architecture specification, with the following limitations:
    11  * The floating point instructions are not supported
     11 * The floating point instructions are supported, FPU exception detection is partially implemented
    1212 * The Mips virtual memory instructions are not supported. The MMU is implemented as an external TLB (SoCLib generic MMU) in the [wiki:Component/VciVcacheWrapper VciVcacheWrapper] component.
    1313
    … …  
    2020 * source:trunk/soclib/soclib/iss/mips32/src/mips32.cpp
    2121 * source:trunk/soclib/soclib/iss/mips32/src/mips32_cp0.cpp
     22 * source:trunk/soclib/soclib/iss/mips32/src/mips32_fpu.cpp
    2223 * source:trunk/soclib/soclib/iss/mips32/src/mips32_hazard.cpp
    2324 * source:trunk/soclib/soclib/iss/mips32/src/mips32_instructions.cpp