Version 1 (modified by 16 years ago) (diff) | ,
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SocLib Components General Index
Processor Functional Description
This component is an ISS (Instruction Set Simulator), which can be wrapped in a CABA or TLM-T Wrapper.
It implements all instructions defined in the MIPS32 architecture specification, with the following limitations:
- The floating point instructions are not supported
- The virtual memory instructions are not supported, as an external TLB (SoCLib generic MMU) is implemented in the VciVcacheWrapper? component.
Both little-endian and big-endian implementations are available.
Component definition & implementation
- source:trunk/soclib/soclib/lib/mips32/metadata/mips32.sd
- source:trunk/soclib/soclib/lib/mips32/include/mips32.h
- source:trunk/soclib/soclib/lib/mips32/src/mips32.cpp
- source:trunk/soclib/soclib/lib/mips32/src/mips32_cp0.cpp
- source:trunk/soclib/soclib/lib/mips32/src/mips32_hazard.cpp
- source:trunk/soclib/soclib/lib/mips32/src/mips32_instructions.cpp
- source:trunk/soclib/soclib/lib/mips32/src/mips32_load_store.cpp
- source:trunk/soclib/soclib/lib/mips32/src/mips32_run.cpp
- source:trunk/soclib/soclib/lib/mips32/src/mips32_special.cpp
- source:trunk/soclib/soclib/lib/mips32/src/mips32_special2cpp
- source:trunk/soclib/soclib/lib/mips32/src/mips32_special3.cpp
Template parameters
This component has no template parameters.
Constructor parameters
Visible registers
The following internal registers define the processor internal state, and can be inspected:
- r_pc : Program counter
- m_ins : Instruction register
- r_gpr[i] : General registers ( 0 < i < 32)
- r_hi & r_lo : Intermediate registers for multiply / divide instructions
- r_cp0[i] : Coprocessor 0 registers (0<=i<32). Implemented values:
- 8: BAR : Bad address register
- 12: SR : Status register
- 13: CR : Cause register
- 14: EPC : Exception PC register
- 15: INFOS : CPU identification number on bits [9:0]
Interrupts
Mips defines 6 interrupts lines. Le lowest number has the hiest priority.
The handling and prioritization of the interrupts is deferred to software.
Ports
None, it is to the wrapper to provide them.