SocLib Components General Index

Ppc Processor Functional Description

This hardware component is a PPC405 processor core.

This ISS uses the ISS2 API and should be wrapped with an VciXcacheWrapper.

The simulation model is actually an instruction set simulator, organised as a two-stage pipeline:

  • First stage: instruction fetch & execute with a possible access to the external data cache.
  • Second stage: read memory access is written back to registers

The main functional specifications are the following:

  • The floating point instructions are not supported
  • There is no TLB, and no hardware support for virtual memory directly in the ISS. Nevertheless, MMU may be supported through the cache.

Component definition

Available in source:trunk/soclib/soclib/iss/metadata/


Ppc405 has no parameters.

Uses( 'common:ppc405')

Ppc405 Processor ISS Implementation

The implementation is in

Template parameters

This component has no template parameters.

Constructor parameters

     const std::string &name,   //  Instance Name
     int  ident);   // processor id


Ppc405 defines two interrupt lines.

  • 0: External interrupt
  • 1: Critical interrupt


None, it is to the wrapper to provide them.

Last modified 13 years ago Last modified on Dec 9, 2009, 10:06:54 AM