| 1 | [wiki:Component SocLib Components General Index] |
| 2 | |
| 3 | = Ppc Processor Functional Description = |
| 4 | |
| 5 | This hardware component is a PPC405 processor core. This is only an ISS, which should be wrapped with an [wiki:Component/IssWrapper IssWrapper]. |
| 6 | |
| 7 | The simulation model is actually an instruction set simulator, organised as a two-stage pipeline: |
| 8 | * First stage: instruction fetch & execute with a possible access to the external data cache. |
| 9 | * Second stage: read memory access is written back to registers |
| 10 | |
| 11 | The main functional specifications are the following: |
| 12 | * The floating point instructions are not supported |
| 13 | * There is no TLB, and no hardware support for virtual memory |
| 14 | |
| 15 | = Component definition = |
| 16 | |
| 17 | Available in source:trunk/soclib/desc/soclib/ppc405.sd |
| 18 | |
| 19 | == Usage == |
| 20 | |
| 21 | Ppc405 has no parameters. |
| 22 | {{{ |
| 23 | Uses( 'ppc405') |
| 24 | }}} |
| 25 | |
| 26 | = Ppc405 Processor ISS Implementation = |
| 27 | |
| 28 | The caba implementation is in |
| 29 | * source:trunk/soclib/systemc/include/common/iss/ppc405.h |
| 30 | * source:trunk/soclib/systemc/include/common/iss/ppc405_ops.inc |
| 31 | * source:trunk/soclib/systemc/src/common/iss/ppc405.cc |
| 32 | * source:trunk/soclib/systemc/src/common/iss/ppc405_instructions.cc |
| 33 | * source:trunk/soclib/systemc/src/common/iss/ppc405_jump_tables.cc |
| 34 | * source:trunk/soclib/systemc/src/common/iss/ppc405_instructions.cc |
| 35 | |
| 36 | == Template parameters == |
| 37 | |
| 38 | This component has no template parameters. |
| 39 | |
| 40 | == Constructor parameters == |
| 41 | {{{ |
| 42 | Ppc405Iss( |
| 43 | sc_module_name name, // Instance Name |
| 44 | int ident); // processor id |
| 45 | }}} |
| 46 | |
| 47 | == Ports == |
| 48 | |
| 49 | None, it is to the wrapper to provide them. |
| 50 | |