Changes between Version 6 and Version 7 of Component/Ppc405


Ignore:
Timestamp:
Feb 9, 2009, 6:40:00 PM (14 years ago)
Author:
Nicolas Pouillon
Comment:

Ppc405 is now Iss2

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  • Component/Ppc405

    v6 v7  
    55This hardware component is a PPC405 processor core.
    66
    7 This ISS uses the [wiki:Component/IssApi ISS API]
    8 and should be wrapped with an [wiki:Component/IssWrapper IssWrapper].
     7This ISS uses the [wiki:Component/Iss2Api ISS2 API]
     8and should be wrapped with an [wiki:Component/VciXcacheWrapper VciXcacheWrapper].
    99
    1010The simulation model is actually an instruction set simulator, organised as a two-stage pipeline:
     
    1414The main functional specifications are the following:
    1515 * The floating point instructions are not supported
    16  * There is no TLB, and no hardware support for virtual memory
     16 * There is no TLB, and no hardware support for virtual memory directly in the ISS. Nevertheless, MMU may be supported through the cache.
    1717
    1818= Component definition =
     
    4343{{{
    4444Ppc405Iss(
    45      sc_module_name name,   //  Instance Name
     45     const std::string &name,   //  Instance Name
    4646     int  ident);   // processor id
    4747}}}