Changes between Version 6 and Version 7 of Component/Ppc405

Timestamp:

Feb 9, 2009, 6:40:00 PM (15 years ago)

Author:

Nicolas Pouillon

Comment:

Ppc405 is now Iss2

Component/Ppc405

@@ -5 +5 @@
 This hardware component is a PPC405 processor core.
 
-This ISS uses the [wiki:Component/IssApi ISS API]
-and should be wrapped with an [wiki:Component/IssWrapper IssWrapper].
+This ISS uses the [wiki:Component/Iss2Api ISS2 API]
+and should be wrapped with an [wiki:Component/VciXcacheWrapper VciXcacheWrapper].
 
 The simulation model is actually an instruction set simulator, organised as a two-stage pipeline:
@@ -14 +14 @@
 The main functional specifications are the following:
  * The floating point instructions are not supported
- * There is no TLB, and no hardware support for virtual memory
+ * There is no TLB, and no hardware support for virtual memory directly in the ISS. Nevertheless, MMU may be supported through the cache.
 
 = Component definition =
@@ -43 +43 @@
 {{{
 Ppc405Iss( 
-     sc_module_name name,   //  Instance Name
+     const std::string &name,   //  Instance Name
      int  ident);   // processor id
 }}}