Changes between Version 2 and Version 3 of Component/ST231
- Timestamp:
- Feb 25, 2010, 10:39:24 AM (14 years ago)
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Component/ST231
v2 v3 5 5 = ST231 Processor Functional Description = 6 6 7 This hardware component is a MicroBlaze processor core as described in [www.xilinx.com/ise/embedded/mb_ref_guide.pdf the Xilinx documentation]. 8 Note that the 9.2 version of ISE contains a pretty major evolution of the MicroBlaze that integrates a MMU, but this is not the version available within SoCLib (at least yet!). 7 The ST231 processor core is an hardware component implementing a 7-stage VLIW processor with register scoreboarding and 32-bit x 32-bit multiplies for integer and fractional data representations. 8 Though a MMU was also added so the ST231 can be used as a host processor, this processor is mostly used in digital video consumer electronics. 9 9 10 This component is an ISS, which should be wrapped with an [wiki:Component/IssWrapper IssWrapper] for integration into a complete platform. 10 11 11 12 This instruction set simulator acts as a slave to the IssWrapper and is organised identically to the 12 13 other Isses available within the library. 13 Currently, the execution timings are pretty rough, and are typically one cycle per instruction.14 15 The support for symetric and asymetric multiprocessing is hardwired using the `fsl` feature of the MicroBlaze.16 The processor number is given at instanciation time, and accessible through `get` on `fsl0`.17 Using other `fsl`s will lead to an abort.18 14 19 15 = Component definition =