30 | | Each channel k has 5 memory-mapped registers : |
31 | | * '''CHBUF_SRC[k]The chbuf descriptor address (CHBUF_DESC), and the number of chained |
32 | | // buffers (CHBUF_NBUFS), as well as the elementary buffer size (BUF_SIZE) |
33 | | // are software parameters that must be written in addressable registers |
34 | | // when launching a transfer between two chbufs. |
35 | | // |
36 | | // |
37 | | // - The elementary buffer size and all buffers base addresses must be multiple |
38 | | // of 4 bytes. If the source and destination buffers are not aligned on a burst |
39 | | // boundary, the DMA controler split the burst in two VCI transactions. |
40 | | // |
41 | | // In order to support various protection mechanisms, for each channel, |
42 | | // the channel addressable registers takes 4K bytes in the address space. |
43 | | // Only 8 address bits are decoded . |
44 | | // - The 5 bits ADDRESS[4:Ø] define the target register (see chbuf_dma.h) |
45 | | // - The 3 bits ADDRESS[14:12] define the selected channel. |
46 | | // |
| 31 | Each channel [k] has 10 memory-mapped 32 bits registers: |
| 32 | * CHBUF_RUN[k] (write-only) : channel activated when writing a non-zero value |
| 33 | * CHBUF_STATUS[k] (read-only) : channel status |
| 34 | * CHBUF_SRC_DESC[k] (read/write) : SRC chbuf descriptor 32 LSB bits physical address |
| 35 | * CHBUF_DST_DESC[k] (read/write) : DST chbuf descriptor 32 LSB bits physical address |
| 36 | * CHBUF_SRC_NBUFS[k] (read/write) : SRC chbuf number of buffers |
| 37 | * CHBUF_DST_NBUFS[k] (read/write) : DST chbuf number of buffers, |
| 38 | * CHBUF_BUF_SIZE[k] (read/write) : buffer size for both source & destination |
| 39 | * CHBUF_PERIOD[k] (read/write) : number of cycles between two status polling |
| 40 | * CHBUF_SRC_EXT[k] (read/write) : SRC chbuf descriptor 32 MSB bits physical address |
| 41 | * CHBUF_DST_EXT[k] (read/write) : DST chbuf descriptor 32 MSB bits physical address |
| 42 | For extensibility issues, you should access the DMA using globally-defined offsets, and you should include file `soclib/chbuf_dma.h` in your software. |
| 43 | In order to support various protection mechanisms, for each channel, the channel addressable registers takes 4K bytes in the address space. |
| 44 | The following address bits are decoded . |
| 45 | * The 5 bits ADDRESS[4:0] define the target register. |
| 46 | * The 3 bits ADDRESS[14:12] define the selected channel. |
48 | | For each channel, the relevant values for the channel status are: |
49 | | * CHANNEL_IDLE : channel not running |
50 | | * CHANNEL_SRC_DESC_ERROR : bus error accessing SRC CHBUF descriptor |
51 | | * CHANNEL_DST_DESC_ERROR : bus error accessing DST CHBUF descriptor |
52 | | * CHANNEL_SRC_DATA_ERROR : bus error accessing SRC CHBUF data |
53 | | * CHANNEL_DST_DATA_ERROR : bus error accessing DST CHBUF data |
54 | | * CHANNEL_BUSY : channel running |
| 48 | For each channel, the relevant values for the channel status are the following: |
| 49 | || Channel Status || value || || |
| 50 | || CHANNEL_IDLE || 0 || channel not running || |
| 51 | || CHANNEL_SRC_DESC_ERROR || 1 || bus error accessing SRC CHBUF descriptor || |
| 52 | || CHANNEL_DST_DESC_ERROR || 2 || bus error accessing DST CHBUF descriptor || |
| 53 | || CHANNEL_SRC_DATA_ERROR || 3 || bus error accessing SRC CHBUF data || |
| 54 | || CHANNEL_DST_DATA_ERROR || 4 || bus error accessing DST CHBUF data || |
| 55 | || CHANNEL_BUSY || >4 || channel running || |
57 | | n error state. The channel can be reset by writing a nul value in register CHBUF_RUN[k], focing channel[k] to IDLE state. |
58 | | // |
59 | | // In order to support multiple simultaneous transactions, the channel |
60 | | // index is transmited in the VCI TRDID field. |
61 | | As the !VciDma component, this component moves data from |
62 | | a source memory buffer to a destination memory buffer. |
63 | | It is both a target and an initiator. |
64 | | * It is addressed as a target to be configured for a transfer. |
65 | | * It is acting as an initiator to do the transfer. |
| 58 | an error state. The channel can be reset by writing a nul value in register CHBUF_RUN[k], focing channel[k] to IDLE state. |
67 | | The !VciMultiDma component supports up to 8 simultaneous DMA transfers, |
68 | | corresponding to 8 independant DMA channels. As there is only one VCI initiator port, the general arbitration policy between the active channels is round-robin. |
69 | | |
70 | | The number of channels (CHANNELS) and the burst length (MAX_BURST_LENGTH) are constructor parameters. The burst length parameter must be multiple of 4 bytes. |
71 | | |
72 | | This component makes the assumption that the VCI RDATA & WDATA fiels have 32 bits. |
73 | | The source buffer base address, the destination buffer base address and the buffer length |
74 | | mus be multiple of 4 bytes. The buffer length is not constrained to be a multiple of |
75 | | the burst length. |
76 | | |
77 | | Each channel has its own set of memory mapped registers, and for each |
78 | | channel a specific IRQ can be optionally asserted when transfer is completed. |
79 | | |
80 | | |
81 | | |
82 | | * '''DMA_SRC[k]''' (Read / Write) |
83 | | It defines the physical address of the source buffer. |
84 | | |
85 | | * '''DMA_DST[k]''' (Read / Write) |
86 | | It defines the physical address of the destination buffer. |
87 | | |
88 | | * '''DMA_LEN[k]''' (Read / Write) |
89 | | A write access defines the length of the transfer (in bytes), and starts the transfer. |
90 | | A read access returns the DMA channel status. The relevant values for the status are: |
91 | | || Cnannel Status || Value || |
92 | | ||DMA_IDLE || 2 || |
93 | | ||DMA_SUCCESS || 0 || |
94 | | ||DMA_READ_ERROR || 1 || |
95 | | ||DMA_WRITE_ERROR || 3 || |
96 | | ||DMA_BUSY || >3 || |
97 | | |
98 | | * '''DMA_RESET[k]''' (Write-only) |
99 | | Writing any value into this pseudo-register makes a clean re-initialisation of the DMA coprocessor: |
100 | | The on-going VCI transaction is completed before the coprocessor returns the IDLE state. |
101 | | This write access must be used by the software ISR to aknowledge the DMA IRQ. |
102 | | |
103 | | * '''DMA_IRQ_DISABLED[k]''' (Read / Write) |
104 | | A non zero value disables the IRQ line. The RESET value is zero. |
105 | | |
106 | | In order to support various protection mechanisms, each channel akes 4K bytes in the address space. The segment size is 32 K bytes, and the segment associated to this peripheral must be aligned on a 32K bytes boundary. Only 8 address bits are decoded : |
107 | | * The five bits ADDRESS[4:0] define the target register. |
108 | | * The three bits ADDRESS[14:12] define the channel index. |
109 | | |
110 | | For extensibility issues, you should access the DMA using globally-defined offsets, and |
111 | | you should include file `soclib/dma.h` in your software, it |
112 | | defines `DMA_SRC`, `DMA_DST`, `DMA_LEN`, `DMA_RESET`, `DMA_IRQ_DISABLED`. |
113 | | |
114 | | This hardware component checks for segmentation violation, and can be used |
115 | | as a default target. |
| 60 | This hardware component checks for segmentation violation, and can be used as a default target. |