wiki:Component/VciI2cInterface

SocLib Components General Index

VciI2cInterface

1) Functional Description

This VCI target is an I2C controller. This hardware component saves in its FIFO all requests then handles them to be transmitted via I2C bus successively. The slave’s address is defined by a base address (I2C controller address on VCI bus) and a size (number of slaves). The I2C controller send an interruption to the processor to inform that data collected from I2C bus is ready. The segments allocated to a given instance of this component are defined in the Mapping Table.

2) Component definition & usage

source:trunk/soclib/soclib/module/internal_component/vci_i2c/caba/metadata/vci_i2c.sd

See SoclibCc/VciParameters

Uses( 'vci_i2c', **vci_parameters )

3) CABA Implementation

CABA sources

CABA Constructor parameters

  • VciI2cInterface
    VciI2cInterface(
    	sc_module_name insname,                 // Component Name
    	const soclib::common::IntTab & index,   // Target Index 
    	const soclib::common::MappingTable &mt, // Mapping Table
    	int PW);                                // Pulse’s Width (SCL)
    

CABA Ports

  • sc_in<bool> p_resetn : System reset
  • sc_in<bool> p_clk : System clock
  • sc_out<bool> p_irq : Interrupts port
  • sc_out<bool> p_full : FIFO is full
  • sc_in<bool> p_sdai : Serial Data in
  • sc_in<bool> p_scli : Serial Clock in
  • sc_out<bool> p_sdao : Serial Data out
  • sc_out<bool> p_sclo : Serial Clock out
  • soclib::caba::VciTarget<vci_param> p_vci : The VCI port

4) TLM-T Implementation

The TLM-T implementation is not available.

Last modified 12 years ago Last modified on Feb 25, 2010, 4:32:20 PM