wiki:Component/VciLocks

SocLib Components General Index

VciLocks

1) Functional Description

This VCI target is a locks controller : In VCI-based systems, it is not anymore possible to "lock the bus" to implement the atomic test & set instructions used for software synchronisation. Therefore, this memory mapped hardware peripheral implements a set of binary locks:

  • Each binary lock is a single flip-flop, but corresponds to 4 bytes in the address space. The segment allocated to this component must be aligned on a 4 bytes boundary. The number of available locks is defined by segment_size / 4.
  • Any read request is interpreted as a test & set operation : the value stored in the addressed flip-flop is returned, and the addressed flip-flop is set to 1.
  • All write request are interpreted as reset : the addressed flip-flop is reset to 0.

This way, a spin lock is implemented as a simple loop waiting to read 0, and the lock release is a simple write operation. This components checks addresses for segmentation violation, and can be used as default target.

2) Component definition & usage

source:trunk/soclib/soclib/module/internal_component/vci_locks/caba/metadata/vci_locks.sd

Uses( 'vci_locks' )

3) CABA Implementation

CABA sources

CABA Constructor parameters

VciLocks(
     sc_module_name name,   // Instance name
     const soclib::common::IntTab &index,   //  Target index
     const soclib::common::MappingTable &mt);   // Mapping Table

CABA Ports

  • sc_in<bool> p_resetn : Global system reset
  • sc_in<bool> p_clk : Global system clock
  • soclib::caba::VciTarget<vci_param> p_vci : The VCI port

4) TLM-DT implementation

TLM-DT sources

TLM-DT Constructor parameters

VciLocks(
     sc_module_name name,   // Instance name
     const soclib::common::IntTab &index,   //  Target index
     const soclib::common::MappingTable &mt);   // Mapping Table

TLM-DT Ports

  • p_vci : VCI target port
Last modified 13 years ago Last modified on Oct 30, 2009, 2:36:55 PM

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