| 5 | | This VCI target is an hardware locks controller. |
| | 7 | This VCI target is a locks controller : In VCI-based systems, it is not anymore possible |
| | 8 | to "lock the bus" to implement the atomic ''test & set'' instructions used for software synchronisation. |
| | 9 | Therefore, this memory mapped hardware peripheral implements a set of binary locks: |
| | 10 | * Each binary lock is a single flip-flop, but corresponds to 4 bytes in the address space. The segment allocated to this component must be aligned on a 4 bytes boundary. |
| | 11 | * Any read request is interpreted as a ''test an set'' operation : the value stored in the addressed flip-flop is returned, and the addressed flip-flop is set to 1. |
| | 12 | * All write request are interpreted as ''reset'' : the the addressed flip-flop is reset to 0. |
| | 13 | This way, a spin lock is implemented as a simple loop waiting to read 0, and the lock release is a simple write operation. |
| | 14 | This components checks addresses for segmentation violation, and can be used as default target. |
| 7 | | VCI-based systems may have some difficulties implementing proper locking of target components |
| 8 | | as this can be done on buses. As a side-effect, locks and other atomic-access-based |
| 9 | | software resources can't be used. This component solves this problem implementing the |
| 10 | | atomic-access-like features on target side. |
| 11 | | |
| 12 | | This components has one bit of information stored on each 32-bit addressable word: |
| 13 | | * When read, its current value is returned, and it is implicitly set to 1 |
| 14 | | * When written to, it is reset to 0. |
| 15 | | |
| 16 | | This way: |
| 17 | | * A spin lock is a simple loop waiting to read 0 |
| 18 | | * Releasing the lock is a simple write operation |
| 19 | | |
| 20 | | = CABA Implementation = |
| | 16 | = !VciLocks CABA Implementation = |
