Changes between Version 4 and Version 5 of Component/Vci Locks


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Timestamp:
May 5, 2007, 5:15:26 PM (17 years ago)
Author:
alain
Comment:

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  • Component/Vci Locks

    v4 v5  
    11= !VciLocks Functional Description =
    22
    3 [wiki:Components SOCLIB COMPONENTS INDEX]
     3[wiki:Component SOCLIB COMPONENTS INDEX]
    44
    55[[Image(VciLocks.png, align=right)]]
    … …  
    88to "lock the bus" to implement the atomic ''test & set'' instructions used for software synchronisation.
    99Therefore, this memory mapped hardware peripheral implements a set of binary locks:
    10  * Each binary lock is a single flip-flop, but corresponds to 4 bytes in the address space. The segment allocated to this component must be aligned on a 4 bytes boundary.
    11  * Any read request is interpreted as a ''test an set'' operation : the value stored in the addressed flip-flop is returned, and the addressed flip-flop is set to 1.
    12  * All write request are interpreted as ''reset'' : the the addressed flip-flop is reset to 0.
     10 * Each binary lock is a single flip-flop, but corresponds to 4 bytes in the address space. The segment allocated to this component must be aligned on a 4 bytes boundary. The number of available locks is defined by segment_size / 4.
     11 * Any read request is interpreted as a ''test & set'' operation : the value stored in the addressed flip-flop is returned, and the addressed flip-flop is set to 1.
     12 * All write request are interpreted as ''reset'' : the addressed flip-flop is reset to 0.
    1313This way, a spin lock is implemented as a simple loop waiting to read 0, and the lock release is a simple write operation.
    1414This components checks addresses for segmentation violation, and can be used as default target.