5 | | This VCI target is an embedded SRAM controller. This hardware component implements up to |
6 | | 16 independent memory segments : Each segment is defined by a BASE address and a SIZE (number of bytes). |
7 | | Both the BASE and the SIZE parameters must be multiple of 4. |
8 | | The segments allocated to a given instance of this component is defined in the mapping table. |
| 5 | This VCI target is an embedded SRAM controller. This hardware component handles |
| 6 | independent memory segments. Each segment is defined by a base address and a size (number of bytes). |
| 7 | Both the base and the size parameters must be multiple of 4. |
| 8 | The segments allocated to a given instance of this component are defined in the MappingTable. |
25 | | sc_module_name name, // Instance name |
26 | | const soclib::common::IntTab &index, // Target index |
27 | | const soclib::common::MappingTable &mt, // Mapping Table |
| 29 | sc_module_name name, // Instance name |
| 30 | const soclib::common::IntTab &index, // Target index |
| 31 | const soclib::common::MappingTable &mt, // Mapping Table |
| 32 | soclib::common::ElfLoader &loader); |
| 33 | }}} |
| 34 | |
| 35 | * Uninitialized !MultiRam: |
| 36 | {{{ |
| 37 | VciMultiRam( |
| 38 | sc_module_name name, // Instance name |
| 39 | const soclib::common::IntTab &index, // Target index |
| 40 | const soclib::common::MappingTable &mt, // Mapping Table |