Changes between Version 2 and Version 3 of Component/Vci Mwmr Controller
- Timestamp:
- Feb 9, 2008, 7:51:28 PM (16 years ago)
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Component/Vci Mwmr Controller
v2 v3 1 1 [wiki:Component SocLib Components General Index] 2 2 3 = !VciMwmrController Functional Description=3 = !VciMwmrController = 4 4 5 This VCI component is both a target and an initiator. 6 * Addressing as a target allows to configure it for a transfer. 7 * Initiator will do the transfer 5 == 1) Functional Description == 8 6 9 This component may handle interfaces to a Fifo-accessed coprocessor. There 10 may be any number of fifos from/to the coprocessor. 7 This VCI component is the hardware part of the MWMR communication middleware. 8 It allows an hardware coprocessor to communicate to one or several MWMR channels. 9 The coprocessor communicates with the MWWR controller through several FIFO interfaces 10 (one FIFO interface per MWMR channel). 11 An internal FSM implements the five steps MWMR communication protocol (5 VCI 12 transactions for one MWMR transaction). 13 It contains as many hardware FiFOs as the number of supported MWMR channels. 14 An MWMMR transaction starts when a Write FIFO is FULL, or when a 15 Read FIFO is empty. The priority policy between the supported channels is Round Robin. 11 16 12 In conjunction with the fifos, there are multiple unidirectionnal 32-bits signals 13 going from/to the coprocessor. 17 This component is both a target and an initiator. 18 * It is addressed as a target to be configured. 19 * It is acting as an initiator to do the MWMR transfers 20 21 Besides the communication channels, this MWMR controller provides a variable number 22 of unidirectionnal 32-bits signals going from/to the coprocessor. 14 23 * from the coprocessor, they are ''status'' registers 15 * to the coprocessor, they are ''config '' registers24 * to the coprocessor, they are ''configuration'' registers 16 25 17 26 This hardware component cheks for segmentation violation, and can be used 18 27 as a default target. 19 28 20 = Memory region layout = 21 29 As a target this component contains the following memory mapped registers: 22 30 * Registers 0 to `MWMR_IOREG_MAX` 23 31 When read from, they reflects status registers, when written to, they reflects the control registers. … … 50 58 A boolean enabling the selected fifo. 51 59 52 = Component usage =53 54 60 For extensibility issues, you should access the !MwmrController using globally-defined offsets. 55 56 61 You should include `soclib/MwmrController.h` from your software, it 57 62 defines all useful offsets and constants. … … 63 68 (add -I/path/to/soclib/include to your compilation command-line) 64 69 65 = Component definition=70 == 2) Component definition & usage == 66 71 67 Available in source:trunk/soclib/module/internal_component/vci_mwmr_controller/caba/metadata/vci_mwmr_controller.sd 68 == Usage == 69 70 !VciMwmrController has two template parameters: VCI ones, and internal fifo maximum depth. It may be used like others, see [wiki:SoclibCc/VciParameters SoclibCc/VciParameters] 72 source:trunk/soclib/soclib/module/internal_component/vci_mwmr_controller/caba/metadata/vci_mwmr_controller.sd 73 See [wiki:SoclibCc/VciParameters SoclibCc/VciParameters] 71 74 {{{ 72 Uses( 'vci_MwmrController', fifo_depth = 32,**vci_parameters )75 Uses( 'vci_MwmrController', **vci_parameters ) 73 76 }}} 74 77 75 = !VciMwmrController CABA Implementation=78 == 3) CABA Implementation == 76 79 77 The caba implementation is in 78 * source:trunk/soclib/module/internal_component/vci_mwmr_controller/caba/source/include/vci_mwmr_controller.h 79 * source:trunk/soclib/module/internal_component/vci_mwmr_controller/caba/source/src/vci_mwmr_controller.cpp 80 === CABA sources === 80 81 81 == Template parameters: == 82 * interface : source:trunk/soclib/soclib/module/internal_component/vci_mwmr_controller/caba/source/include/vci_mwmr_controller.h 83 * implementation : source:trunk/soclib/soclib/module/internal_component/vci_mwmr_controller/caba/source/src/vci_mwmr_controller.cpp 82 84 83 * The VCI parameters 84 * The fifo depth 85 86 == Constructor parameters == 85 === CABA Constructor === 87 86 {{{ 88 87 VciMwmrController( 89 sc_module_name name, 90 const IntTab &index, 91 const MappingTable &mt, 92 const size_t plaps, # Default timeout between two access retries to a given MWMR 93 const size_t n_to_coproc, # \ Cardinal of fifos 94 const size_t n_from_coproc,# / interfacing the coprocessor 95 const size_t n_config, # \ Cardinal of registers 96 const size_t n_status ); # / (sideband signals) 88 sc_module_name name, // instance name 89 const IntTab &index, // VCI target index 90 const MappingTable &mt, // mapping table 91 const size_t plaps, // Default timeout between two access retries to a given channel 92 const size_t n_to_coproc, // number of read MWMR channels 93 const size_t n_from_coproc, // number of write MWMR channels 94 const size_t n_config, // number of configuration registers 95 const size_t n_status, // number of status registers 96 const size_t fifo_depth); // hardware FIFOs depth 97 97 }}} 98 98 99 == Ports==99 === CABA Ports === 100 100 101 101 * sc_in<bool> '''p_resetn''' : Global system reset … … 108 108 * sc_in<uint32_t> '''p_status[]''' : Status ports 109 109 110 == 4) TLM-T Implementation == 111 112 The TLM-T implementation is not available yet.
