Changes between Version 3 and Version 4 of Component/Vci Mwmr Controller
- Timestamp:
- Feb 9, 2008, 8:21:43 PM (17 years ago)
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Component/Vci Mwmr Controller
v3 v4 11 11 An internal FSM implements the five steps MWMR communication protocol (5 VCI 12 12 transactions for one MWMR transaction). 13 It contains as many hardware FiFOs as the number of supported MWMR channels.13 This component contains as many hardware FiFOs as the number of supported MWMR channels. 14 14 An MWMMR transaction starts when a Write FIFO is FULL, or when a 15 15 Read FIFO is empty. The priority policy between the supported channels is Round Robin. … … 32 32 33 33 * `MWMR_RESET` 34 W hen written to, this register resets the current state of the controller, flushing all fifos andconfiguration.34 Writing into this register resets the current state of the controller, flushing all hardware FIFOs and the MWMR controller configuration. 35 35 36 36 * `MWMR_CONFIG_FIFO_WAY` and `MWMR_CONFIG_FIFO_NO` 37 Used to designate the currently configured fifo. WAY may be `MWMR_TO_COPROC` or `MWMR_FROM_COPROC`, NO may be any of available fifos in the selected way. 37 Used to designate the currently configured MWMR channel. WAY may be `MWMR_TO_COPROC` or `MWMR_FROM_COPROC`, 38 NO may be any MWMR channel in the selected way. 38 39 39 40 * `MWMR_CONFIG_STATE_ADDR` 40 Sets the address of state field for the selected fifo's state block.41 Sets the address of state field for the selected MWMR channel. 41 42 42 43 * `MWMR_CONFIG_OFFSET_ADDR` 43 Sets the address of read/write pointer field for the selected fifo's state block.44 Sets the address of read/write pointer field for the selected MWMR channel. 44 45 45 46 * `MWMR_CONFIG_LOCK_ADDR` 46 Sets the address of lock for the selected fifo's state block.47 Sets the address of the lock protecting the selected MWMR channel. 47 48 48 49 * `MWMR_CONFIG_DEPTH` 49 Sets the depth of the selected fifo.50 Sets the depth of the selected MWMR channel. 50 51 51 52 * `MWMR_CONFIG_WIDTH` 52 Sets the width of the selected fifo. This will determine the atomic transfer block size. This must be multiple of 4.53 Sets the width of the selected MWMR channel. This will determine the atomic transfer block size. This must be multiple of 4 bytes. 53 54 54 55 * `MWMR_CONFIG_BASE_ADDR` 55 Sets the address of data for the selected fifo.56 Sets the address of the data buffer for the selected MWMR channel. 56 57 57 58 * `MWMR_CONFIG_RUNNING` 58 A boolean enabling the selected fifo.59 A boolean enabling the selected MWMR channel. 59 60 60 61 For extensibility issues, you should access the !MwmrController using globally-defined offsets.
