SocLib Components General Index


1) Functional Description

This hardware component is a generic system bus respecting the VCI advanced protocol. As any bus, it supports one single transaction at a given time. It reproduces accurately the timing behaviour (both throughput & latency) of the PIbus.

It gives the system designer a generic "communication black-box" with a parametrized number of VCI initiator ports (NB_INITIATOR), and a parameterized number of VCI target ports (NB_TARGET). It can be used to build a "flat" interconnect, where all VCI initiators and targets are identified by a single index:

  • The VCI targets must be indexed from 0 to (NB_TARGET - 1).
  • The VCI initiators must be indexed from 0 to (NB_INITIATOR - 1).

When several initiators try to use the bus, the arbitration policy is round-robin.

As any VCI advanced compliant interconnect, this component uses the MSB bits of the VCI ADDRESS field to route the command packets to the proper target, thanks to a routing table, implemented as a ROM. This routing table is build by the constructor from the informations stored in the mapping table.

2) Component definition and usage


Uses( 'vci_vgsb' )

3) CABA Implementation

CABA sources

CABA Constructor parameters

     sc_module_name name,                    //  instance name
     const soclib::common::MappingTable &mt, // mapping table
     size_t nb_initiator,                    // number of initiators
     size_t nb_target);                      // number of targets

CABA Ports

  • sc_in<bool> p_resetn : Global system reset
  • sc_in<bool> p_clk : Global system clock
  • soclib::caba::VciTarget<vci_param> p_from_initiator[] : Ports from VCI initiators
  • soclib::caba::VciInitiator<vci_param> p_to_target[] : Ports to VCI targets

4) TLM-T Implementation

Not available

Last modified 13 years ago Last modified on Oct 11, 2009, 9:48:16 PM