Changes between Version 8 and Version 9 of Component/Vci Xcache Wrapper
- Timestamp:
- Aug 25, 2008, 5:34:30 PM (16 years ago)
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Component/Vci Xcache Wrapper
v8 v9 14 14 15 15 16 * The !VciXcacheWrapper provides the same functionalities asthe previous !VciXcache component. It has an higher simulation speed, and supports associativity (for both the instruction and data caches).17 * The !VciVcacheWrapper implementa generic paged MMU (see below).18 * The !VciCcacheWrapper implement a directory-based cache coherence protocol (see below).16 * The !VciXcacheWrapper (in short Xcache) replace the previous !VciXcache component. It has an higher simulation speed, and supports associativity (for both the instruction and data caches). 17 * The !VciVcacheWrapper (in short Vcache) has the same functionnalities as the Xcache, and implements a generic paged MMU (see below). 18 * The !VciCcacheWrapper (in short CC_Xcache) has the same functionnalities as the Xcache, and implement a directory-based cache coherence protocol (see below). 19 19 * The !VciCcVcachewrapper supports both the generic MMU and the cache coherence. 20 20 … … 60 60 === Generic MMU === 61 61 62 The Vcache and CC_Vcache components implement a generic MMU service, that can be used by all the single instruction issue 32 bits processors available in the SoCLib platform. 63 In the Vcache and CC_Vcache components, the cachability (for both instruction & data accesses) can be defined 64 by software - on a per-logical-page basis) through the cacheability attribut contained in each page descriptor. 65 But the cachability can also be controlled (on a per-physical-segment basis) through the mapping table. 66 62 67 === Cache Coherence === 63 68 … … 98 103 99 104 === CABA constructor parameters === 100 '''Xcache & Vcache'''105 '''Xcache''' 101 106 {{{ 102 107 VciXcacheWrapper( … … 112 117 size_t dcache_sets ); 113 118 }}} 114 '''CC_Xcache & CC_Vcache''' 115 {{{ 116 VciXcacheWrapper( 119 '''Vcache''' 120 {{{ 121 VciVcacheWrapper( 122 sc_module_name insname, 123 int proc_id, 124 const soclib::common::MappingTable &mt, 125 const soclib::common::IntTab &index, 126 size_t itlb_m_ways, 127 size_t itlb_m_sets, 128 size_t itlb_k_ways, 129 size_t itlb_k_sets, 130 size_t dtlb_m_ways, 131 size_t dtlb_m_sets, 132 size_t dtlb_k_ways, 133 size_t dtlb_k_sets, 134 size_t page_m_nbits, 135 size_t page_k_nbits, 136 size_t icache_lines, 137 size_t icache_words, 138 size_t icache_sets, 139 size_t dcache_lines, 140 size_t dcache_words 141 size_t dcache_sets ); 142 }}} 143 '''CC_Xcache''' 144 {{{ 145 VciCcXcacheWrapper( 117 146 sc_module_name insname, 118 147 int proc_id, … … 127 156 size_t dcache_sets ); 128 157 }}} 158 '''CC_Vcache''' 159 {{{ 160 VciCcVcacheWrapper( 161 sc_module_name insname, 162 int proc_id, 163 const soclib::common::MappingTable &mt, 164 const soclib::common::IntTab &initiator_index, 165 const soclib::common::IntTab &target_index, 166 size_t itlb_m_ways, 167 size_t itlb_m_sets, 168 size_t itlb_k_ways, 169 size_t itlb_k_sets, 170 size_t dtlb_m_ways, 171 size_t dtlb_m_sets, 172 size_t dtlb_k_ways, 173 size_t dtlb_k_sets, 174 size_t page_m_nbits, 175 size_t page_k_nbits, 176 size_t icache_lines, 177 size_t icache_words, 178 size_t icache_sets, 179 size_t dcache_lines, 180 size_t dcache_words 181 size_t dcache_sets ); 182 }}} 183 129 184 === CABA ports === 130 185