Changes between Version 10 and Version 11 of Component/Vci Xicu

Timestamp:

Oct 31, 2010, 9:32:52 PM (15 years ago)

Author:

alain

Comment:

--

Component/Vci Xicu

@@ -75 +75 @@
 
 This register is decremented by 1 on each clock's raising edge. When it gets to 0, the value is reset to the corresponding period register value (PTI_PER[PTI–INDEX]), and the corresponding timer interrupt line is asserted until acknowledged. Decrementation goes on whether interrupt is acknowledged or not. 
- * On write : Resets the current value of TIMER[PTI_INDEX]. 
-Writing a value greater than PTI_PER[PTI_INDEX] in this register has no particular side-effect: value will normally decrement to 0 and then be reset to PTI_PER[PTI_INDEX] when wrapping. 
+ * On write : Resets the current value of TIMER[PTI_INDEX]. Writing a value greater than PTI_PER[PTI_INDEX] in this register has no particular side-effect: value will normally decrement to 0 and then be reset to PTI_PER[PTI_INDEX] when wrapping. 
  * On read : Gets the current value of TIMER[PTI_INDEX]. 
 
@@ -85 +84 @@
  * On read : Acknowledges the interrupt associated to TIMER[PTI_INDEX]. Read value has no useful meaning. 
 
-'''MSK_PTI[OUT_INDEX] : Programmable Timet Mask for IRQ[OUT_INDEX]'''
+'''MSK_PTI[OUT_INDEX] : Programmable Timer Mask for IRQ[OUT_INDEX]'''
 
-Each bit in this register is a mask for the corresponding TI%ER IRQ. A 1 in bit x enables the Timer as an interrupt source for IRQ[OUT_INDEX]. 
+Each bit in this register is a mask for the corresponding timer IRQ. A 1 in bit x enables the timer x as an interrupt source for IRQ[OUT_INDEX]. 
  * On write : Sets the current mask 
  * On read : Gets the current mask 
+
+'''MSK_PTI_ENABLE[OUT_INDEX] : Programmable Timer Mask Enabler for IRQ[OUT_INDEX]'''
+
+Each bit written here unmasks the corresponding timer IRQ. Writing a 1 in bit x enables the timer as an interrupt source for IRQ[OUT_INDEX]. 
+ * On write : ORs MSK_PTI[OUT_INDEX] with the written value. 
+ * On read : Unsupported 
+
+'''MSK_PTI_DISABLE[OUT_INDEX] : Programmable Timer Mask Disabler for IRQ[OUT_INDEX]'''
+
+Each bit written here masks the corresponding timer IRQ. Writing a 1 in bit x edisables the timer as an interrupt source for IRQ[OUT_INDEX]. 
+ * On write : ANDs MSK_PTI[OUT_INDEX] with the complement of the written value. 
+ * On read : Unsupported 
+
+'''PTI_ACTIVE[OUT_INDEX] : Current Unmasked Timer IRQs for IRQ[OUT_INDEX]'''
+
+Each bit read here corresponds to an active and unmasked timer IRQ, according to current 
+global timer status and MSK_PTI[OUT_INDEX]. 
+ * On write : Unsupported 
+ * On read : Gets the current timer status for IRQ[OUT_INDEX]. 
+
+'''MSK_HWI[OUT_INDEX] : Hardware Interrupts Mask for IRQ[OUT_INDEX]'''
+
+Each bit in this register is a mask for the corresponding hardware IRQ. A 1 in bit x enables the 
+hardware interrupt x as an interrupt source for IRQ[OUT_INDEX]. 
+ * On write : Sets the current mask 
+ * On read : Gets the current mask 
+
 
 Complete specification is in [attachment:xicu-1.0.pdf].