Changes between Version 11 and Version 12 of Component/Vci Xicu


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Timestamp:
Oct 31, 2010, 10:11:30 PM (15 years ago)
Author:
alain
Comment:

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  • Component/Vci Xicu

    v11 v12  
    6262'''WTI_REG[WTI_INDEX] : Write-Triggered Interrupt Register'''
    6363
    64 This register retains the value written. It can be used as a mailbox between the interrupt source and the target if here is only one source. In case of several sources, two different sources may write sequentially to this register, overwriting the value present in register.
     64This register retains the value written. It can be used as a mailbox between the software interrupt source and the target if here is only one source. In case of several sources, two different sources may write sequentially to this register, overwriting the value present in register.
    6565 * On write : Raises WTI[WTI_INDEX]
    6666 * On read : Acknowledges WTI[WTI_INDEX]
    … …  
    9292'''MSK_PTI_ENABLE[OUT_INDEX] : Programmable Timer Mask Enabler for IRQ[OUT_INDEX]'''
    9393
    94 Each bit written here unmasks the corresponding timer IRQ. Writing a 1 in bit x enables the timer as an interrupt source for IRQ[OUT_INDEX].
     94Each bit written here unmasks the corresponding timer IRQ. Writing a 1 in bit x enables the timer x as an interrupt source for IRQ[OUT_INDEX].
    9595 * On write : ORs MSK_PTI[OUT_INDEX] with the written value.
    9696 * On read : Unsupported
    … …  
    9898'''MSK_PTI_DISABLE[OUT_INDEX] : Programmable Timer Mask Disabler for IRQ[OUT_INDEX]'''
    9999
    100 Each bit written here masks the corresponding timer IRQ. Writing a 1 in bit x edisables the timer as an interrupt source for IRQ[OUT_INDEX].
     100Each bit written here masks the corresponding timer IRQ. Writing a 1 in bit x disables the timer x as an interrupt source for IRQ[OUT_INDEX].
    101101 * On write : ANDs MSK_PTI[OUT_INDEX] with the complement of the written value.
    102102 * On read : Unsupported
    … …  
    111111'''MSK_HWI[OUT_INDEX] : Hardware Interrupts Mask for IRQ[OUT_INDEX]'''
    112112
    113 Each bit in this register is a mask for the corresponding hardware IRQ. A 1 in bit x enables the
     113Each bit in this register is a mask for the corresponding hardware interrupt. A 1 in bit x enables the
    114114hardware interrupt x as an interrupt source for IRQ[OUT_INDEX].
    115115 * On write : Sets the current mask
    116116 * On read : Gets the current mask
    117117
     118'''MSK_HWI_ENABLE[OUT_INDEX] : Hardware Interrupt Mask Enabler for IRQ[OUT_INDEX]'''
     119
     120Each bit written here unmasks the corresponding hardware interrupt. Writing a 1 in bit x enables the hardware interrupt x as an interrupt source for IRQ[OUT_INDEX].
     121 * On write : ORs MSK_PTI[OUT_INDEX] with the written value.
     122 * On read : Unsupported
     123
     124'''MSK_HWI_DISABLE[OUT_INDEX] : Hardware Interrupt Mask Disabler for IRQ[OUT_INDEX]'''
     125
     126Each bit written here masks the corresponding hardware interrupt. Writing a 1 in bit x disables the hardware interrupt x as an interrupt source for IRQ[OUT_INDEX].
     127 * On write : ANDs MSK_PTI[OUT_INDEX] with the complement of the written value.
     128 * On read : Unsupported
     129
     130'''HWI_ACTIVE[OUT_INDEX] : Current Unmasked Hardware Interrupts for IRQ[OUT_INDEX]'''
     131
     132Each bit read here corresponds to an active and unmasked hardware interrupt, according to current
     133global hardware interrupt status and MSK_HWI[OUT_INDEX].
     134 * On write : Unsupported
     135 * On read : Gets the current hardware interrupts status for IRQ[OUT_INDEX].
     136
     137'''MSK_WTI[OUT_INDEX] : Write-Triggered Interrupts Mask for IRQ[OUT_INDEX]'''
     138
     139Each bit in this register is a mask for the corresponding software interrupt. A 1 in bit x enables the
     140software interrupt x as an interrupt source for IRQ[OUT_INDEX].
     141 * On write : Sets the current mask
     142 * On read : Gets the current mask
     143
     144'''MSK_WTI_ENABLE[OUT_INDEX] : Write-Triggered Interrupt Mask Enabler for IRQ[OUT_INDEX]'''
     145
     146Each bit written here unmasks the corresponding software interrupt. Writing a 1 in bit x enables the software interrupt x as an interrupt source for IRQ[OUT_INDEX].
     147 * On write : ORs MSK_PTI[OUT_INDEX] with the written value.
     148 * On read : Unsupported
     149
     150'''MSK_WTI_DISABLE[OUT_INDEX] : Write-Triggered Interrupt Mask Disabler for IRQ[OUT_INDEX]'''
     151
     152Each bit written here masks the corresponding software interrupt. Writing a 1 in bit x disables the software interrupt x as an interrupt source for IRQ[OUT_INDEX].
     153 * On write : ANDs MSK_PTI[OUT_INDEX] with the complement of the written value.
     154 * On read : Unsupported
     155
     156'''WTI_ACTIVE[OUT_INDEX] : Current Unmasked Write-Triggered Interrupts for IRQ[OUT_INDEX]'''
     157
     158Each bit read here corresponds to an active and unmasked software interrupt, according to current
     159global software interrupt status and MSK_WTI[OUT_INDEX].
     160 * On write : Unsupported
     161 * On read : Gets the current software interrupts status for IRQ[OUT_INDEX].
     162
     163'''PRIO[OUT_INDEX] : Priority Encoder for IRQ[OUT_INDEX]'''
     164
     165This register holds the index of the highest priority, active and unmasked interrupt for each source type.
     166 * On write : Unsupported
     167 * On read : Get the three highest-priority active interrupt indexes for IRQ[OUT_INDEX].
     168
     169||000||PRIO_WTI||000||PRIO_HWI||000||PRIO_PTI||00000||W||H||T||
     170
     171 * Bit T is set if there is at least one unmasked timer interrupt.
     172 * Bit H is set if there is at least one unmasked hardware interrupt.
     173 * Bit W is set if there is at least one unmasked software interrupt.
    118174
    119175Complete specification is in [attachment:xicu-1.0.pdf].