Changes between Version 4 and Version 5 of Component/Vci Xicu


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Timestamp:
Oct 30, 2010, 9:40:44 PM (14 years ago)
Author:
alain
Comment:

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  • Component/Vci Xicu

    v4 v5  
    88a vectorized interrupt controller, a timer controller, and an Inter-processor interrupt controller.
    99
    10 It can concentrate up to
    11  * 32 independent interrupt lines
    12  * 32 independent timers
    13  * 32 IPI registers
    14 multiplexing to up to 32 output lines
    15 
     10This controller is an interrupt hub, concentrating 3 types of interrupts:
     11 * up to 32 internal programmable timer interrupts (PTI),
     12 * up to 32 external hardware interrupt lines (HWI),
     13 * up to 32 internal write-triggered interrupts (WTI).
     14All these interrupt sources can be routed to up to 32 interrupt outputs. Each output can
     15mask individual interrupt sources.
     16Priority between interrupt source types is left to the handling operating system. Priority
     17of interrupts inside an interrupt source type is from the lowestIdx(highest priority) to
     18the highestIdx(lower priority).
    1619
    1720Complete specification is in [attachment:xicu-1.0.pdf].
     21
     22=== 1.1) Constructor Parameters ===
     23
     24All hardware implementations of this component may not implement all the up-to-32
     25PTI (Timers), up-to-32 HWI lines, up-to-32 WTI registers and up-to-32 OUTPUTlines.
     26The following parameters allow the system designer to get just the needed hardware.
     27
     28 * pti count (in range0..32): number of programmable timers
     29 * hwi count (in range0..32): number of external hardware interrupt lines
     30 * wti count (in range0..32): number of write-triggered interrupt sources
     31 * irqcount (in range1..32): number of output interrupt lines
     32
     33=== 1.2) Programmers's View ===
     34
     35This component can be mapped anywhere in the address space, on a 4-KiBboundary. This component is 32-bit data-word based: arbitrary byte access is not supported.
     3612 lower address lines are used the following way:
     37
     38|| FUNC   || INDEX || 00 ||
     39|| 5 bits || 5bits ||    ||
     40
     41 * '''FUNC''' indicates the functionnality
     42 * '''IDX''' index in the range 0...31
     43
     44||MODE|| Register         || FUNC  || INDEX   ||
     45||R/W || WTI_REG          || 00000 || WTI_IDX ||
     46||R/W || PTI_PER          || 00001 || PTI_IDX ||
     47||R/W || PTI_VAL          || 00010 || PTI_IDX ||
     48||W   || PTI_ACK          || 00011 || PTI_IDX ||
     49
     50||R/W || MSK_PTI          || 00100 || 0UT_IDX ||
     51||W   || MSK_PTI_ENABLE   || 00101 || OUT_IDX ||
     52||W   || MSK_PTI_DISABLE  || 00110 || OUT_IDX ||
     53||R   || PTI_ACTIVE       || 00110 || OUT_IDX ||
     54
     55||R/W || MSK_HWI          || 01000 || OUT_IDX ||
     56||W   || MSK_HWI_ENABLE   || 01001 || OUT_IDX ||
     57||W   || MSK_HWI_DISABLE  || 01010 || OUT_IDX ||
     58||R   || HTI_ACTIVE       || 01010 || OUT_IDX ||
     59
     60||R/W || MSK_WTI          || 01100 || OUT_IDX ||
     61||W   || MSK_WTI_ENABLE   || 01101 || OUT_IDX ||
     62||W   || MSK_WTI_DISABLE  || 01110 || OUT_IDX ||
     63||R   || WTI_ACTIVE       || 01110 || OUT_IDX ||
     64
     65||R/W || WTI_REG_WTI_IDX  || 00000 || WTI_IDX ||
     66||R/W || WTI_REG_WTI_IDX  || 00000 || WTI_IDX ||
     67||R/W || WTI_REG_WTI_IDX  || 00000 || WTI_IDX ||
     68||R/W || WTI_REG_WTI_IDX  || 00000 || WTI_IDX ||
     69||R/W || WTI_REG_WTI_IDX  || 00000 || WTI_IDX ||
     70||R/W || WTI_REG_WTI_IDX  || 00000 || WTI_IDX ||
     71||R/W || WTI_REG_WTI_IDX  || 00000 || WTI_IDX ||
     72||R/W || WTI_REG_WTI_IDX  || 00000 || WTI_IDX ||
     73||R/W || WTI_REG_WTI_IDX  || 00000 || WTI_IDX ||
     74||R/W || WTI_REG_WTI_IDX  || 00000 || WTI_IDX ||
     75||R/W || WTI_REG_WTI_IDX  || 00000 || WTI_IDX ||
    1876
    1977== 2) Component definition & usage ==