Changes between Version 112 and Version 113 of Component


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Timestamp:
Mar 25, 2010, 11:30:24 AM (14 years ago)
Author:
Nicolas Pouillon
Comment:

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  • Component

    v112 v113  
     1[[PageOutline()]]
    12
    2 = Processor ISS (Instruction Set Simulator) =
     3The library contains all needed parts to create a fully working VirtualPrototype.
    34
    4 These ISS must be wrapped in a CABA, TLM, or TLMDT wrapper to be used in a SoCLib platforms.
    5 Example of such a wrapper is the [wiki:Component/VciXcacheWrapper VciXcacheWrapper] component.
     5Most simulation models connect around an on-chip bus.
     6It is either a NoC or a simpler BUS or crossbar. Most
     7SoCLib components are using the VCI on-chip-bus protocol. This
     8makes the components easily interoperable. Moreover, VCI is simple
     9enough to ease integration of new components, without forbidding
     10translation of VCI to other protocols.
     11See [#OnChipBusNoCProtocoladapters On-Chip-Bus/NoC Protocol adapters].
    612
     13
     14Available models can be split up in categories
     15
     16= On-Chip-Bus/NoC implementations =
     17
     18Several NoC implementations exist in SoCLib, providing interconnection for most of other modules.
     19
     20Two main types of interconnects are available:
     21 * Virtual interconnects, implementing a typical behavior without an existing hardware equivalent.
     22   This abstraction from an actual implementation makes simulation faster, without
     23   making performance evaluation worse.
     24  * [wiki:Component/VciVgmn VciVgmn] acts as a typical worm-holeNoC. (M->N communication, switched network)
     25  * [wiki:Component/VciVgsb VciVgsb] acts as a classical BUS. (1 at-a-time communication, synchronous response)
     26 * Actual interconnects, which can be implemented as RTL
     27  * BUSes
     28   * [wiki:Component/VciPiBus VciPibus] : A VCI compliant PIBUS implementation.
     29   * [wiki:Component/VciAvalonBus  VciAvalonBus]  : A VCI compliant AVALON bus interconnect.
     30  * Crossbars:
     31   * [wiki:Component/VciLocalCrossbar VciLocalCrossbar] : A VCI compliant crossbar.
     32  * 2D-meshes:
     33   * [wiki:Component/VciDspin VciDspin] : A VCI compliant DSPIN micro-network.
     34   * [wiki:Component/VirtualDspinNetwork VirtualDspinNetwork] : A VCI compliant Dspin micro-network with virtual channels.
     35   * [wiki:Component/VciAnoc VciAnoc] : A VCI compliant ANOC micro-network.
     36  * Ring-based:
     37   * [wiki:Component/VciSimpleRingNetwork VciSimpleRingNetwork] : A VCI compliant ring interconnect.
     38   * [wiki:Component/VciLocalRingNetwork  VciLocalRingNetwork]  : A VCI compliant ring interconnect.
     39
     40= On-Chip-Bus/NoC Protocol adapters =
     41
     42 * [wiki:Component/VciPCI VciPCI] : A bridge to the PCI bus
     43
     44= OCB/NoC configuration utilities =
     45
     46 * [wiki:Component/MappingTable MappingTable] : A tool to declare and list all memory segments used in a platform and to define the memory mapping.
     47
     48= Processor + cache =
     49
     50In SoCLib, processor+cache bundles are designed as two distinct entities. This has several advantages:
     51 * Many CPU cores out there are just the same instruction set with variations on the implementation (pipeline stages, cache, coherency, coprocessors, …)
     52 * Modeling a cache alone is easier
     53 * Modeling an ISS alone is easier
     54 * Instrumentation tools can be factored-out (gdb, profiling, …)
     55
     56SoCLib provides different caches, with different features.
     57All caches can be used with all ISSes, some features
     58may just be unavailable in certain configurations (eg. not all CPU support MMU-aware caches).
     59
     60Cache models:
     61 * [wiki:Component/VciXcacheWrapper VciXcacheWrapper] : A generic, VCI compliant, cache controller for Iss2Api processors
     62 * [wiki:Component/VciXcacheWrapper VciVcacheWrapper] : A generic, VCI compliant, cache controller for Iss2Api processors supporting virtual memory mapping
     63
     64ISS models:
    765 * [wiki:Component/Iss2Api processors using the Iss2API]
    866  * [wiki:Component/Mips32 Mips32]
    … …  
    1270  * [wiki:Component/lm32 Lattice Mico 32]
    1371  * [wiki:Component/NIOSII NiosII]
     72  * [wiki:Component/IssIss2 IssIss2] : This wrapper may be necessary to use
     73    the following [wiki:Component/IssApi IssApi]-compliant ISSes
     74    (!IssApi is deprecated. New ISSes should implement the Iss2Api)
     75   * [wiki:Component/MicroBlaze MicroBlaze]
     76   * [wiki:Component/ST231 ST231]
     77   * [wiki:Component/TMS320C62 TMS320C62]
     78   * [wiki:Component/MPC7447A MPC7447A]
    1479
    15  * [wiki:Component/IssApi processors using the IssAPI]
    16   * [wiki:Component/MicroBlaze MicroBlaze]
    17   * [wiki:Component/ARM7TDMI ARM7TDMI]
    18   * [wiki:Component/ARM966 ARM966]
    19   * [wiki:Component/ST231 ST231]
    20   * [wiki:Component/TMS320C62 TMS320C62]
    21   * [wiki:Component/MPC7447A MPC7447A]
     80ISS instrumenting tools:
     81  * [wiki:Tools/GdbServer] : A GDB-server wrapper, for any ISS.
     82  * [wiki:Tools/IssMemchecker] : A wrapper providing walgrind-like features, for any ISS.
    2283
    23   * [wiki:Tools/GdbServer] : A GDB-server wrapper, for any ISS using the Iss2API.
    24   * [wiki:Component/IssIss2 IssIss2] : Utility wrapper to use any [wiki:Component/IssApi IssApi] compliant ISS in an [wiki:Component/Iss2Api Iss2Api] [#IssWrapperscaches wrapper]
     84= Memories =
    2585
    26 = Components =
     86 * [wiki:Component/VciRom VciRom] : A multi-segment embedded ROM controller
     87 * [wiki:Component/VciMultiRam VciRam] : A multi-segment embedded RAM controller
     88 * [wiki:Component/VciSimpleRam VciSimpleRam] : A multi-segment embedded RAM controller with parameterized latency
    2789
    28 == VCI Targets ==
    29  
    30  * [wiki:Component/VciMultiRam VciRam] : A multi-segment embedded Ram controller
    31  * [wiki:Component/VciSimpleRam VciSimpleRam] : A multi-segment embedded Ram controller with parameterized latency
     90 * [wiki:Component/VciLocks VciLocks] : A memory mapped locks controller (memory with implicit test-and-set)
     91
     92Memory loading is done through [wiki:Component/Loader Loader] : A binary-file loader (ELF, COFF, plain)
     93
     94= IO Controllers =
     95
     96Character devices:
    3297 * [wiki:Component/VciMultiTty VciMultiTty] : A memory mapped multi-TTY controller
    33  * [wiki:Component/VciXicu VciXicu] : A memory mapped Hardware interrupt + Timer + IPI controller
     98 * [wiki:Component/VciLogConsole VciLogConsole] : A memory-mapped text log sink, for debugging purposes
     99 * [wiki:Component/VciI2cInterface VciI2cInterface] : An I2C bus controller.
     100
     101Block devices (with DMA):
     102 * [wiki:Component/VciFdAccess VciFdAccess] : A file system access controller
     103 * [wiki:Component/VciBlockDevice VciBlockDevice] : A block device controller
     104
     105Other:
     106 * [wiki:Component/VciFrameBuffer VciFrameBuffer] : A frame buffer for YUV or RVB image display.
     107
     108= Internal controllers =
     109
    34110 * [wiki:Component/VciMultiTimer VciTimer] : A memory mapped timer controller
    35111 * [wiki:Component/VciIcu VciIcu] : A memory mapped interrupt controller
    36  * [wiki:Component/VciLocks VciLocks] : A memory mapped locks controller
    37  * [wiki:Component/VciPCI VciPCI] : A bridge to the PCI bus
    38  * [wiki:Component/VciLogConsole VciLogConsole] : A memory-mapped text log sink
    39  * [wiki:Component/VciSimHelper VciSimHelper] : A memory-mapped simulation control tool
    40112 * [wiki:Component/Mailbox Mailbox] : A mailbox component allows several processors to communicate via an interrupt mecanism
    41  * [wiki:Component/VciFrameBuffer VciFrameBuffer] : A frame buffer for YUV or RVB image display.
    42  * [wiki:Component/VciI2cInterface VciI2cInterface] : An I2C bus controller.
    43113
    44 == VCI Initiators ==
     114 * [wiki:Component/VciXicu VciXicu] : A memory mapped Hardware interrupt + Timer + IPI controller (all the 3 above controllers in 1)
    45115
    46  * Iss Wrappers (caches)
    47   * [wiki:Component/VciXcacheWrapper VciXcacheWrapper] : A generic, VCI compliant, cache controller for [#ProcessorISSInstructionSetSimulator Iss2Api] processors
    48   * [wiki:Component/VciXcacheWrapper VciVcacheWrapper] : A generic, VCI compliant, cache controller for [#ProcessorISSInstructionSetSimulator Iss2Api] processors supporting virtual memory
    49  * Other initiators
    50   * [wiki:Component/VciXcache VciXcache] : A cache controller for 32 bits [#ProcessorISSInstructionSetSimulator IssApi] processors (deprecated)
    51   * [wiki:Component/VciDma VciDma] : A DMA engine
    52   * [wiki:Component/VciFdAccess VciFdAccess] : A file system access controller
    53   * [wiki:Component/VciBlockDevice VciBlockDevice] : A block device controller
    54   * [wiki:Component/VciMwmrController VciMwmrController] : A Mwmr channels controller
    55   * [wiki:Component/VciMwmrControllerLf VciMwmrControllerLf] : Another Mwmr channels controller
     116 * [wiki:Component/VciDma VciDma] : A DMA engine
    56117
    57 == VCI Interconnects ==
     118 * [wiki:Component/VciMwmrController VciMwmrController] : A Mwmr channels controller
     119 * [wiki:Component/VciMwmrControllerLf VciMwmrControllerLf] : Another Mwmr channels controller, with a lock-free software protocol
    58120
    59  * [wiki:Component/VciVgmn VciVgmn] : A VCI compliant generic micro-network.
    60  * [wiki:Component/VciVgsb VciVgsb] : A VCI compliant generic system bus.
    61  * [wiki:Component/VciLocalCrossbar VciLocalCrossbar] : A VCI compliant crossbar.
    62  * [wiki:Component/VciPiBus VciPibus] : A VCI compliant PIBUS implementation.
    63  * [wiki:Component/VciDspin VciDspin] : A VCI compliant DSPIN micro-network.
    64  * [wiki:Component/VciSimpleRingNetwork VciSimpleRingNetwork] : A VCI compliant ring interconnect.
    65  * [wiki:Component/VciLocalRingNetwork  VciLocalRingNetwork]  : A VCI compliant ring interconnect.
    66  * [wiki:Component/VciAvalonBus  VciAvalonBus]  : A VCI compliant AVALON bus interconnect.
    67  * [wiki:Component/VciAnoc VciAnoc] : A VCI compliant ANOC micro-network.
    68  * [wiki:Component/VirtualDspinNetwork VirtualDspinNetwork] : A VCI compliant Dspin micro-network with virtual channels.
    69  * [wiki:Component/VciInitiatorTransactor VciInitiatorTransactor] : A VCI CABA Initiator compliant VCI TLM-DT Initiator.
    70  * [wiki:Component/VciTargetTransactor VciTargetTransactor] : A VCI CABA Target compliant VCI TLM-DT Target.
    71 
    72 == VCI Utilities ==
    73 
    74  * [wiki:Component/VciLogger VciLogger] : A VCI spy, useful for debugging network messages
    75 
    76 = Dedicated coprocessors =
     121= Dedicated coprocessors, not necessarily connected to On-Chip-Bus =
    77122
    78123  * [wiki:Component/Tc4200 Tc4200] : A WiMAX LDPC decoder
    … …  
    88133  * [wiki:Component/Tc1700 Tc1700] : A triple mode turbo decoder (3GPP-LTE, HSPA, WiMAX)
    89134
    90 = Common utilities =
     135= Debugging tools =
    91136
    92  * [wiki:Component/MappingTable MappingTable] : A tool to declare and list all memory segments used in a platform and to define the memory mapping.
    93  * [wiki:Component/Loader Loader] : A binary-file loader (ELF, COFF, plain)
     137== Simulation controller utilities ==
     138
     139 * [wiki:Component/VciSimHelper VciSimHelper] : A memory-mapped simulation control tool, can call `sc_stop` or `exit` upon specific memory access
     140
     141== VCI debugging ==
     142
     143 * [wiki:Component/VciLogger VciLogger] : A VCI spy, useful for debugging network messages
     144
     145= Simulation MoC wrappers =
     146
     147Some components are just syntactical wrappers in order to mix CABA and TLM-DT simulation models:
     148
     149 * [wiki:Component/VciInitiatorTransactor VciInitiatorTransactor] : A VCI CABA Initiator compliant VCI TLM-DT Initiator.
     150 * [wiki:Component/VciTargetTransactor VciTargetTransactor] : A VCI CABA Target compliant VCI TLM-DT Target.
     151
     152= Component factored-out code library =
     153
     154These are common parts of modules that have been factored-out
     155to ease current and future components writing. Their usage
     156is not mandatory for newly-written components, but is useful.
     157
    94158 * [wiki:Component/VciTargetFsm VciTargetFsm] : A generic CABA submodule for handling the VCI fsm part of a target components, so that you can focus on the functionality
    95159 * [wiki:Component/TtyWrapper TtyWrapper] : A simulator-side TTY abstraction tool, used by the [wiki:Component/VciMultiTty VciMultiTty] component
    96160 * [wiki:Component/ProcessWrapper ProcessWrapper] : A simulator-side fork/exec abstraction tool, with process' stdin/stdout communication
    97161 * [wiki:Component/FbController FbController] : A simulator-side framebuffer abstraction tool
    98