wiki:Component

Version 113 (modified by Nicolas Pouillon, 15 years ago) (diff)

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  1. On-Chip-Bus/NoC implementations
  2. On-Chip-Bus/NoC Protocol adapters
  3. OCB/NoC configuration utilities
  4. Processor + cache
  5. Memories
  6. IO Controllers
  7. Internal controllers
  8. Dedicated coprocessors, not necessarily connected to On-Chip-Bus
  9. Debugging tools
    1. Simulation controller utilities
    2. VCI debugging
  10. Simulation MoC wrappers
  11. Component factored-out code library

The library contains all needed parts to create a fully working VirtualPrototype.

Most simulation models connect around an on-chip bus. It is either a NoC or a simpler BUS or crossbar. Most SoCLib components are using the VCI on-chip-bus protocol. This makes the components easily interoperable. Moreover, VCI is simple enough to ease integration of new components, without forbidding translation of VCI to other protocols. See On-Chip-Bus/NoC Protocol adapters.

Available models can be split up in categories

On-Chip-Bus/NoC implementations

Several NoC implementations exist in SoCLib, providing interconnection for most of other modules.

Two main types of interconnects are available:

  • Virtual interconnects, implementing a typical behavior without an existing hardware equivalent. This abstraction from an actual implementation makes simulation faster, without making performance evaluation worse.
    • VciVgmn acts as a typical worm-holeNoC. (M->N communication, switched network)
    • VciVgsb acts as a classical BUS. (1 at-a-time communication, synchronous response)
  • Actual interconnects, which can be implemented as RTL

On-Chip-Bus/NoC Protocol adapters

  • VciPCI : A bridge to the PCI bus

OCB/NoC configuration utilities

  • MappingTable : A tool to declare and list all memory segments used in a platform and to define the memory mapping.

Processor + cache

In SoCLib, processor+cache bundles are designed as two distinct entities. This has several advantages:

  • Many CPU cores out there are just the same instruction set with variations on the implementation (pipeline stages, cache, coherency, coprocessors, …)
  • Modeling a cache alone is easier
  • Modeling an ISS alone is easier
  • Instrumentation tools can be factored-out (gdb, profiling, …)

SoCLib provides different caches, with different features. All caches can be used with all ISSes, some features may just be unavailable in certain configurations (eg. not all CPU support MMU-aware caches).

Cache models:

  • VciXcacheWrapper : A generic, VCI compliant, cache controller for Iss2Api processors
  • VciVcacheWrapper : A generic, VCI compliant, cache controller for Iss2Api processors supporting virtual memory mapping

ISS models:

ISS instrumenting tools:

Memories

  • VciRom? : A multi-segment embedded ROM controller
  • VciRam : A multi-segment embedded RAM controller
  • VciSimpleRam : A multi-segment embedded RAM controller with parameterized latency
  • VciLocks : A memory mapped locks controller (memory with implicit test-and-set)

Memory loading is done through Loader : A binary-file loader (ELF, COFF, plain)

IO Controllers

Character devices:

Block devices (with DMA):

Other:

Internal controllers

  • VciTimer : A memory mapped timer controller
  • VciIcu : A memory mapped interrupt controller
  • Mailbox : A mailbox component allows several processors to communicate via an interrupt mecanism
  • VciXicu : A memory mapped Hardware interrupt + Timer + IPI controller (all the 3 above controllers in 1)

Dedicated coprocessors, not necessarily connected to On-Chip-Bus

Debugging tools

Simulation controller utilities

  • VciSimHelper : A memory-mapped simulation control tool, can call sc_stop or exit upon specific memory access

VCI debugging

  • VciLogger : A VCI spy, useful for debugging network messages

Simulation MoC wrappers

Some components are just syntactical wrappers in order to mix CABA and TLM-DT simulation models:

Component factored-out code library

These are common parts of modules that have been factored-out to ease current and future components writing. Their usage is not mandatory for newly-written components, but is useful.

  • VciTargetFsm : A generic CABA submodule for handling the VCI fsm part of a target components, so that you can focus on the functionality
  • TtyWrapper : A simulator-side TTY abstraction tool, used by the VciMultiTty component
  • ProcessWrapper : A simulator-side fork/exec abstraction tool, with process' stdin/stdout communication
  • FbController : A simulator-side framebuffer abstraction tool