SocLib Components General Index

Processor Functional Description

This hardware component is a Sparc v8 processor core.

This ISS uses the ISS2 API and can be wrapped in a CABA or TLM-T Wrapper.

It implements all instructions defined in the Sparc v8 architecture specification, with the following limitations:

  • LDSTUB, SWAP and alternate versions work only on a word granularity (see below)
  • the ASI is currently not supported
  • an optional FP is provided through a compilation flag (FPU, enabled by default)
  • gdb server support is under development.

Component definition & implementation

Template parameters

This component has one template parameter :

  • NWIN (int) : the number of windows. By default : 8


Sparc V8 defines 4 interrupts lines.


None, it is to the wrapper to provide them.


LDSTUB and SWAP support

SoCLib infrastructure doesn't support directly SWAP and LDSTUB instructions. Thus they are emulated through SC and LL extended accesses. When executed, the infrastructure verify that they succeeded. If not, they may either trap or be automatically re-executed until successfull execution. The compilation flag SWAP_TRAPS decides which strategy to use.

Warnings :

  • when automatic re-execution is choosen, the system may deadlock.
  • these instructions are only supported on a word granularity : ensure that every variables involved in SWAP and LDSTUB access are in different word

Compiling programs for Sparc v8 with SoCLib

Before compiling a program for the Sparc v8 with the SoCLib framework you will need to define some system variables (usually on the ~/.soclib/soft_compilers.conf) needed to find the Sparc compiler. Below you have an example:

sparc_CC_PREFIX = sparc-unknown-elf-
sparc_CFLAGS = -O2 -g -mcpu=v8 -mfpu  -msoft-quad-float 
sparc_LDFLAGS = 
Last modified 14 years ago Last modified on Apr 27, 2009, 6:20:44 PM