Changes between Version 9 and Version 10 of Soclib Cc/And Modelsim
- Timestamp:
- Jun 14, 2010, 8:50:56 PM (15 years ago)
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Soclib Cc/And Modelsim
v9 v10 19 19 * Select modules and dependancies from a platform description file, 20 20 * Explicitly instantiate C++ templates, 21 * Call the C++ compiler. Only this step is implemented in `sccom`. 21 * Call the C++ compiler. Only this step is implemented in `sccom`, 22 * Call the vhdl or verilog compiler: `vcom` and `vlog`. 22 23 23 24 The flow is as in the picture: … … 42 43 * the path to !ModelSim's SystemC implementation 43 44 * used flags 44 * object file names pattern in sccom workdirectory45 * object file names pattern in sccom `work` directory 45 46 46 47 For all these, we must create 3 new configurations in soclib-cc's … … 51 52 52 53 {{{ 54 #!python 53 55 # Definition of the compiler used for ModelSim-usable SoCLib components. 54 56 # We use sccom for components compilation and linkage, gcc/g++ for utilities … … 62 64 tool_CC_LINKER = 'sccom', 63 65 tool_CXX_LINKER = 'sccom', 66 tool_VHDL = 'vcom', 67 tool_VERILOG = 'vlog', 64 68 # Modelsim cant do parallel builds :'( 65 69 max_processes = 1, … … 68 72 # Special features, it has a -link invocation needed at end... 69 73 libs = ['-link'], 74 # VHDL compilation flags 75 vflags = ['-05', '-quiet', '-check-synthesis'], 70 76 ) 71 77 … … 107 113 There is no `sc_main()` function in modelsim-based simulators. The top 108 114 module must be a `sc_module` with no interfaces. This probably needs a 109 rewrite of your netlists. 115 rewrite of your netlists. (Note: If you use DSX-generated netlists, 116 this is done transparently) 110 117 111 If you use DSX-generated netlists, this is done transparently. 118 = Component Metadata = 119 120 RTL modules, exactly like their caba counterparts, have their own metadata files. 121 Caba modules can use RTL ones as dependancies. 112 122 113 123 = Usage = … … 130 140 131 141 It contains: 132 ` fifo_gen`::142 `rtl:fifo_gen`:: 133 143 The VHDL component writing to the Fifo 134 ` fifo_gen_wrapper`::144 `caba:fifo_gen`:: 135 145 The VHDL/SystemC wrapper to export `fifo_gen` to the SystemC world 136 ` fifo_reader`::146 `caba:fifo_reader`:: 137 147 A SystemC component reading from the fifo 138 ` topcell`::148 `caba:topcell`:: 139 149 A SystemC component implementing the topcell 140 ` system_driver`::150 `caba:system_driver`:: 141 151 A SystemC component controlling `reset` and `clock` signals 142 152 … … 144 154 * Reset the work directory, to make sure, 145 155 {{{ 146 $ rm -rf work transcript modelsim.ini fifo_gen_wrapper/fifo_gen.hvsim.wlf156 $ rm -rf work transcript modelsim.ini vsim.wlf 147 157 }}} 148 158 * Initialize modelsim `work` directory, … … 151 161 $ vmap work work 152 162 }}} 153 * Compile the VHDL module with vcom.154 {{{155 $ vcom fifo_gen/fifo_gen.vhd156 }}}157 * Generate the SystemC wrapper of the `fifo_gen` VHDL module with `scgenmod`158 {{{159 $ scgenmod -sc_uint -bool fifo_gen > fifo_gen_wrapper/fifo_gen.h160 }}}161 163 * Compile the SystemC system driver with soclib-cc, all dependancies are pulled with it. 162 `.sd` metadata are needed (even for the VHDL/SystemC wrapper ), see in tarball.164 `.sd` metadata are needed (even for the VHDL/SystemC wrapper and VHDL modules), see in tarball. 163 165 {{{ 164 166 $ soclib-cc -1 caba:system_driver -t modelsim -v -o sccom-link.o … … 166 168 * Open modelsim with the platform 167 169 {{{ 168 $ vsim - novopt -sclib work system_driver170 $ vsim -sclib work system_driver 169 171 }}} 170 172
