Changes between Version 29 and Version 30 of Wiki Start
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- Jan 31, 2008, 1:21:12 PM (17 years ago)
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Wiki Start
v29 v30 1 {{{ 2 #!html 3 <h1 style="text-align: center; color: blue">Welcome to SoCLib project home page</h1> 4 }}} 1 5 2 Welcome to SoCLib's development Trac 6 ---- 3 7 4 [[PageOutline]] 8 = Goals = 5 9 6 = A) SoCLib Library = 10 * Build an open platform for modeling and simulation of multi-processors system on chip, that can be used by both universities and industrial companies. 11 * The core of the platform is a library of simulation models for virtual components (IP cores), with a guaranteed path to silicon. 12 * Create the largest possible cooperation project at European level, in order to share the development costs. 7 13 8 * [wiki:Component SoCLib Components General Index] : contains documentation about the hardware components (IP cores) available in the SoCLib library. 9 * [wiki:AddComponent Adding new components to the library] : the rules to follow to add a new IP core to the library. 14 = Technical features = 10 15 11 = B) SoCLib Tools = 16 The main concern is true interoperability between the SoCLib IP cores : 17 * All simulation models written in SystemC 18 * Two well defined abstraction levels have been defined : 19 * CABA (Cycle Accurate / Bit Accurate) 20 * TLM-T (Transaction Level Modeling with Time) 21 * All SoCLib components respect the VCI communication protocol. 12 22 13 * [https://www-asim.lip6.fr/trac/dsx DSX] : Design Space Exploration tool 14 * [https://www-asim.lip6.fr/trac/systemcass SystemCASS] : Fast SystemC simulation kernel 15 * [https://www-asim.lip6.fr/trac/socview SoCView] : Simulation kernel for debug and instrumentation 16 * [https://www-asim.lip6.fr/trac/mutekh Mutek] : OS kernel for embedded MPSoCs 23 = Principles = 17 24 18 = C) SoCLib Documentation=25 === Openness === 19 26 20 == Installation, usage == 27 All simulation models are distributed as open source and available to all academic institutions and industrial company 21 28 22 * [wiki:InstallationNotes Installation Notes] : how to install the SoCLib platform on your computer 23 * SoclibCc is the current build system for SoCLib platforms 29 === Path to silicon === 24 30 25 == Writing and design guides == 31 A synthesizable RTL model must exist for each SoCLib component, in order to guarantee a path to silicon for any system designed with the SoCLib library. 26 32 27 * [wiki:WritingRules/General General SoCLib Rules] : general rules regarding the SoCLib components. 28 * [wiki:WritingRules/Caba CABA Writing Rules] : rules to write CABA simulation models. 29 * [wiki:WritingRules/Tlmt TLM-T Writing Rules] : rules to write TLM-T simulation models. 30 * [wiki:WritingRules/RISC Processor Modeling] : a general method to write generic processor models. 33 === Business model === 31 34 32 == Miscelaneous == 35 The RTL synthesizable models are NOT part of the SoCLib library, in order to preserve the IP providers business. 33 36 34 * [wiki:WritingRules/TLMT Critères Pour Plate-Forme TLM-T] : criteria defined for writing TLM-T simulation models. 35 * [attachment:SOCLIB_licences.pdf Comparaison licences LGPL & BSD] 36 * [wiki:SoclibCc/DesignGuide SoclibCc/DesignGuide] is an attempt to justify the choices made in soclib-cc 37 === European scale === 37 38 38 = D) SoCLib project = 39 The SoCLib project was launched and is supported by the French CNRS (Centre National de la Recherche Scientifique), but is now part of the EUROSOC network. 39 40 40 * Here are the [wiki:Models Models of documents to be used] 41 * Here are the [wiki:Compte-Rendus Minutes of the SoCLib meetings] 42 * Here is the archive of the development mailing-list : http://www.soclib.fr/wws 43 * You may follow contractual roadmaps on the [anr:WikiStart ANR/SoCLib project's Trac]. 41 = Partners = 44 42 43 6 industrial companies and 11 academic laboratories are contributing to the French SoCLib project : 44 45 * [http://www.magillem.com/ Magillem Design Services] 46 * [http://www.silicomp.fr/ SILICOMP] 47 * [http://www.st.com/stonline/fr/index.htm STMicrelectronics] 48 * [http://www.thalesonline.com/ Thales Communications] 49 * [http://www.thomson.net/GlobalEnglish/Pages/default.aspx Thomson R&D France] 50 * [http://www.turboconcept.com/index.php TurboConcept] 51 52 * [http://www-list.cea.fr/ CEA-LIST] Saclay 53 * [http://www-leti.cea.fr/scripts/home/publigen/content/templates/show.asp?P=235&L=FR&MASTER=MASTER_WWWLETIHOME CEA-LETI] Grenoble 54 * [http://www.citi.insa-lyon.fr/ CITI] Lyon 55 * [http://www.enst.fr/ ENST] Paris 56 * [http://www.inria.fr/saclay/ INRIA Futurs] Saclay 57 * [http://www.irisa.fr/home_html IRISA] Rennes 58 * [http://web.univ-ubs.fr/lester/www-lester/Index.php Lester] Lorient 59 * [http://www.lip6.fr/fr/index.php LIP6] Paris 60 * [http://www.lis.inpg.fr/ LIS] Grenoble 61 * [http://www.lisif.jussieu.fr/ LISIF] Paris 62 * [http://tima.imag.fr/ TIMA] Grenoble 63 64 65 ---- 66 67 68 = Get your own copy = 69 70 First, you have to create an account, so, if you haven’t already done it, please register! 71 72 {{{ 73 #!html 74 <form method="post" action="http://www.soclib.fr/cgi-bin/soclib_register"> 75 <table border="0" cellpadding="5" cellspacing="0"> 76 <tr> 77 <td align="right" valign="center"><font face="Verdana, Arial, Helvetica, sans-serif" size="2">E-mail:</font></td> 78 <td> 79 <input type="text" name="email" size="45" maxlength="255"> 80 </td> 81 <td height="32"> </td> 82 <td height="32"> <input type=submit name="register" value="Submit request"></td> 83 </tr> 84 </table> 85 </form> 86 }}} 87 88 Please note that this e-mail will be your login ID! 89 90 You may also want to sign-up for the developers mailing list dev@soclib.fr, to do so please visit this [http://www.soclib.fr/wws/info/dev link]. 91 92 93 If you need write access or for any other problem please [mailto:wahid.bahroun@lip6.fr?subject=SoCLib%20Request contact me]. 94 95 96 ---- 97 98 Then you’ll have to setup your environment and install the needed tools. 99 100 You’ll find all the necessary informations on the [https://www.soclib.fr/trac/dev/wiki/Start SoCLib development trac page].