| 10 | | * Build an open platform for modeling and simulation of multi-processors system on chip, that can be used by both universities and industrial companies. |
| 11 | | * The core of the platform is a library of simulation models for virtual components (IP cores), with a guaranteed path to silicon. |
| 12 | | * Create the largest possible cooperation project at European level, in order to share the development costs. |
| | 10 | * SoCLib is an open platform for virtual prototyping of multi-processors system on chip (MP-SoC). |
| | 11 | * The core of the platform is a library of SystemC simulation models for virtual components (IP cores), with a guaranteed path to silicon. |
| | 12 | * The project is funded by the french ''Agence Nationale pour la Recherche''. |
| | 13 | * 6 industrial companies and 11 laboratories are working together to build this platform |
| | 14 | * [http://www.magillem.com/ Magillem Design Services] |
| | 15 | * [http://www.silicomp.fr/ SILICOMP] |
| | 16 | * [http://www.st.com/stonline/fr/index.htm STMicrelectronics] |
| | 17 | * [http://www.thalesonline.com/ Thales Communications] |
| | 18 | * [http://www.thomson.net/GlobalEnglish/Pages/default.aspx Thomson R&D France] |
| | 19 | * [http://www.turboconcept.com/index.php TurboConcept] |
| | 20 | * [http://www-list.cea.fr/ CEA-LIST] Saclay |
| | 21 | * [http://www-leti.cea.fr/scripts/home/publigen/content/templates/show.asp?P=235&L=FR&MASTER=MASTER_WWWLETIHOME CEA-LETI] Grenoble |
| | 22 | * [http://www.citi.insa-lyon.fr/ CITI] Lyon |
| | 23 | * [http://www.enst.fr/ ENST] Paris |
| | 24 | * [http://www.inria.fr/saclay/ INRIA Futurs] Saclay |
| | 25 | * [http://www.irisa.fr/home_html IRISA] Rennes |
| | 26 | * [http://web.univ-ubs.fr/lester/www-lester/Index.php Lester] Lorient |
| | 27 | * [http://www.lip6.fr/fr/index.php LIP6] Paris |
| | 28 | * [http://www.lis.inpg.fr/ LIS] Grenoble |
| | 29 | * [http://www.lisif.jussieu.fr/ LISIF] Paris |
| | 30 | * [http://tima.imag.fr/ TIMA] Grenoble |
| 17 | | * All simulation models written in SystemC |
| 18 | | * Two well defined abstraction levels have been defined : |
| 19 | | * CABA (Cycle Accurate / Bit Accurate) |
| 20 | | * TLM-T (Transaction Level Modeling with Time) |
| 21 | | * All SoCLib components respect the VCI communication protocol. |
| | 35 | * All simulation models are written in SystemC |
| | 36 | * All SoCLib components respect the VCI /OCP communication protocol. |
| | 37 | * Two types of models are available for each IPcore : CABA (Cycle Accurate / Bit Accurate), and TLM-T (Transaction Level Modeling with Time) |
| 25 | | === Openness === |
| 26 | | |
| 27 | | All simulation models are distributed as open source and available to all academic institutions and industrial company |
| 28 | | |
| 29 | | === Path to silicon === |
| 30 | | |
| 31 | | A synthesizable RTL model must exist for each SoCLib component, in order to guarantee a path to silicon for any system designed with the SoCLib library. |
| 32 | | |
| 33 | | === Business model === |
| 34 | | |
| 35 | | The RTL synthesizable models are NOT part of the SoCLib library, in order to preserve the IP providers business. |
| 36 | | |
| 37 | | === European scale === |
| 38 | | |
| 39 | | The SoCLib project was launched and is supported by the French CNRS (Centre National de la Recherche Scientifique), but is now part of the EUROSOC network. |
| 40 | | |
| 41 | | = Partners = |
| 42 | | |
| 43 | | 6 industrial companies and 11 academic laboratories are contributing to the French SoCLib project : |
| 44 | | |
| 45 | | * [http://www.magillem.com/ Magillem Design Services] |
| 46 | | * [http://www.silicomp.fr/ SILICOMP] |
| 47 | | * [http://www.st.com/stonline/fr/index.htm STMicrelectronics] |
| 48 | | * [http://www.thalesonline.com/ Thales Communications] |
| 49 | | * [http://www.thomson.net/GlobalEnglish/Pages/default.aspx Thomson R&D France] |
| 50 | | * [http://www.turboconcept.com/index.php TurboConcept] |
| 51 | | |
| 52 | | * [http://www-list.cea.fr/ CEA-LIST] Saclay |
| 53 | | * [http://www-leti.cea.fr/scripts/home/publigen/content/templates/show.asp?P=235&L=FR&MASTER=MASTER_WWWLETIHOME CEA-LETI] Grenoble |
| 54 | | * [http://www.citi.insa-lyon.fr/ CITI] Lyon |
| 55 | | * [http://www.enst.fr/ ENST] Paris |
| 56 | | * [http://www.inria.fr/saclay/ INRIA Futurs] Saclay |
| 57 | | * [http://www.irisa.fr/home_html IRISA] Rennes |
| 58 | | * [http://web.univ-ubs.fr/lester/www-lester/Index.php Lester] Lorient |
| 59 | | * [http://www.lip6.fr/fr/index.php LIP6] Paris |
| 60 | | * [http://www.lis.inpg.fr/ LIS] Grenoble |
| 61 | | * [http://www.lisif.jussieu.fr/ LISIF] Paris |
| 62 | | * [http://tima.imag.fr/ TIMA] Grenoble |
| 63 | | |
| | 41 | * All simulation models and most associated tools are distributed as free software. |
| | 42 | * The SoClib documentation can be accessed [https://www.soclib.fr/trac/dev/wiki/Start here] |
| | 43 | * To actually download one or several SoClib tools or component, you must register below. |
| | 44 | * For each SoCLib component, a synthesizable RTL model is available, in order to guarantee a path to silicon, but this RTL model is NOT part of the SoCLib library, in order to preserve the IP providers business. |
