| | 1 | [wiki:Component SocLib Components General Index] |
| | 2 | |
| | 3 | = Processor Functional Description = |
| | 4 | |
| | 5 | This component is an ISS (Instruction Set Simulator), which can be wrapped in a CABA or TLM-T [wiki:Component/VciXcacheWrapper Wrapper]. |
| | 6 | |
| | 7 | It implements all instructions defined in the MIPS32 architecture specification, with the following limitations: |
| | 8 | * The floating point instructions are not supported |
| | 9 | * The virtual memory instructions are not supported, as an external TLB (SoCLib generic MMU) is implemented in the [wiki:Component/VciVcacheWrapper VciVcacheWrapper] component. |
| | 10 | |
| | 11 | Both little-endian and big-endian implementations are available. |
| | 12 | |
| | 13 | = Component definition & implementation = |
| | 14 | |
| | 15 | * source:trunk/soclib/soclib/lib/mips32/metadata/mips32.sd |
| | 16 | * source:trunk/soclib/soclib/lib/mips32/include/mips32.h |
| | 17 | * source:trunk/soclib/soclib/lib/mips32/src/mips32.cpp |
| | 18 | * source:trunk/soclib/soclib/lib/mips32/src/mips32_cp0.cpp |
| | 19 | * source:trunk/soclib/soclib/lib/mips32/src/mips32_hazard.cpp |
| | 20 | * source:trunk/soclib/soclib/lib/mips32/src/mips32_instructions.cpp |
| | 21 | * source:trunk/soclib/soclib/lib/mips32/src/mips32_load_store.cpp |
| | 22 | * source:trunk/soclib/soclib/lib/mips32/src/mips32_run.cpp |
| | 23 | * source:trunk/soclib/soclib/lib/mips32/src/mips32_special.cpp |
| | 24 | * source:trunk/soclib/soclib/lib/mips32/src/mips32_special2cpp |
| | 25 | * source:trunk/soclib/soclib/lib/mips32/src/mips32_special3.cpp |
| | 26 | |
| | 27 | == Template parameters == |
| | 28 | |
| | 29 | This component has no template parameters. |
| | 30 | |
| | 31 | == Constructor parameters == |
| | 32 | |
| | 33 | == Visible registers == |
| | 34 | |
| | 35 | The following internal registers define the processor internal state, and can be inspected: |
| | 36 | * r_pc : Program counter |
| | 37 | * m_ins : Instruction register |
| | 38 | * r_gpr[i] : General registers ( 0 < i < 32) |
| | 39 | * r_hi & r_lo : Intermediate registers for multiply / divide instructions |
| | 40 | * r_cp0[i] : Coprocessor 0 registers (0<=i<32). Implemented values: |
| | 41 | * 8: BAR : Bad address register |
| | 42 | * 12: SR : Status register |
| | 43 | * 13: CR : Cause register |
| | 44 | * 14: EPC : Exception PC register |
| | 45 | * 15: INFOS : CPU identification number on bits ![9:0] |
| | 46 | |
| | 47 | == Interrupts == |
| | 48 | |
| | 49 | Mips defines 6 interrupts lines. ~~Le lowest number has the hiest priority.~~ |
| | 50 | The handling and prioritization of the interrupts is deferred to software. |
| | 51 | |
| | 52 | == Ports == |
| | 53 | |
| | 54 | None, it is to the wrapper to provide them. |
| | 55 | |
